PCI-SIO4 User Manual
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787
19
D7
Reset Zilog for Channel 3-4 (Pulsed)
Writing a ‘1’ to this bit will cause the channel 3-4 Zilog Z16C30 USC to be
reset. This bit is a self-timed pulse; therefore, it is not necessary for software to
return to clear this bit, it will clear itself.
Note:
After power up and after any reset to this component, the next access
to channel 3 or channel 4 USC must be a write of 0x00 to offset 0x00 of
channel 3 USC.
D8
Channel 4 Tx FIFO Empty
(TRUE == 0)
D9
Channel 4 Tx FIFO Almost Empty
(TRUE == 0)
D10
Channel 4 Tx FIFO Almost Full
(TRUE == 0)
D11
Channel 4 Tx FIFO Full
(TRUE == 0)
D12
Channel 4 Rx FIFO Empty
(TRUE == 0)
D13
Channel 4 Rx FIFO Almost Empty
(TRUE == 0)
D14
Channel 4 Rx FIFO Almost Full
(TRUE == 0)
D15
Channel 4 Rx FIFO Full
(TRUE == 0)
The FIFO status flags are active low indicators of the current FIFO status. These flags are
continuously being updated every 33ns. A value of ‘0’ indicates that the current status is true and
a value of ‘1’ indicates that it is not true. There are only 5 valid combinations for each nibble
(D8..D11 or D12..D15). These combinations are as follows:
0xC
1100
Almost Empty and Empty
0xD
1101
Almost Empty but not Empty
0xF
1111
In between Almost Empty and Almost Full
0xB
1011
Almost Full but not full
0x3
0011
Almost Full and Full
2.1.20 C
HANNEL
1
S
YNC
D
ETECT
:
(LOC
0
X
50)
D0..7
Channel 1 Sync Detected Data
The data in this register is used to watch the Rx data as it is being loaded into the
main Rx FIFO. If the data being loaded into the FIFO for this channel matches
this data, then an
interrupt request will be generated to the interrupt
logic. An
actual interrupt to the host
will only occur if this
interrupt source is enable in the
interrupt control register.
2.1.21 C
HANNEL
2
S
YNC
D
ETECT
:
(LOC
0
X
54)
D0..7
Channel 2 Sync Detected Data
The data in this register is used to watch the Rx data as it is being loaded into the
main Rx FIFO. If the data being loaded into the FIFO for this channel
matches
this data, then an
interrupt request will be generated
to the interrupt
logic. An actual interrupt to the host will only occur if this
interrupt
source is enable in the interrupt control register.
2.1.22 C
HANNEL
3
S
YNC
D
ETECT
:
(LOC
0
X
58)
D0..7
Channel 3 Sync Detected Data
The data in this register is used to watch the Rx data as it is being loaded in to the
main Rx FIFO. If the data being loaded into the FIFO for this channel matches
this data, then an interrupt request will be generated to the interrupt logic. An
