60 SBC622 Hardware Reference Manual
All
GPIO
inputs
are
double
sampled
at
33
MHz
before
being
used
by
any
internal
logic
of
the
CPLD.
For
valid
operation,
input
states
must
be
valid
for
longer
than
33
nS;
pulses
shorter
than
this
may
be
missed
due
to
the
sampling
of
the
inputs
at
33
MHz.
If
rise
and
fall
times
of
the
GPIO
are
slow
(>10
μ
S),
then
edge
mode
should
not
be
used
as
any
noise
on
the
edges
can
cause
false
triggering.
On
really
slow
edges,
software
may
need
to
filter
the
inputs.
3.2.31 GPIO Out Register (0x640)
This
holds
the
GPIO
out
data.
NOTE
This register is only cleared on a power cycle.
3.2.32 GPIO In Register (0x641)
This
reflects
the
current
state
of
the
GPIO
pins
regardless
of
whether
they
are
configured
as
inputs
or
outputs.
Table 3-15 GPIO Out Register (0x640)
Bit GPIO
Pin
D7 GPIO7
D6 GPIO6
D5 GPIO5
D4 GPIO4
D3 GPIO3
D2 GPIO2
D1 GPIO1
D0 GPIO0
Table 3-16 GPIO In Register (0x641)
Bit GPIO
Pin
D7 GPIO7
D6 GPIO6
D5 GPIO5
D4 GPIO4
D3 GPIO3
D2 GPIO2
D1 GPIO1
D0 GPIO0
Содержание OpenVPX VPXcel6 SBC622
Страница 2: ...Document History Hardware Reference Document Number 500 9300527818 000 Rev B March 18 2011 ...
Страница 30: ...30 SBC622 Hardware Reference Manual Figure 1 2 SBC622 in Chassis VPX Backplane SBC622 inserted into Chassis ...
Страница 33: ...Installation and Setup 33 Figure 1 3 PMC Installed onto 2 PMC Site Model F ...
Страница 37: ...Installation and Setup 37 Figure 1 5 Front Panel SBC622 Isometric View Convection cooled F F ...
