GE OpenVPX VPXcel6 SBC622, Справочник по аппаратуре

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58 SBC622 Hardware Reference Manual
The ʺ IRQ Enable ʺ bit must be set to a ʺ 1 ʺ for the timer to be able to generate an
interrupt. Each timer has an independently selectable clock source which is
selected by the bit pattern in the ʺ Timer x Clock Select ʺ field as follows:
The ʺ Read Timer ʺ bit selects between reading the current timer value or reading
the timer load value when the timer data is read. Setting this bit to ʺ 0 ʺ will enable
the reading of the current timer value. Setting this bit to a ʺ 1 ʺ will enable the
reading of the value that was loaded into the timer.
When the timer generates an interrupt, the ʺ Interrupt ʺ bit is read as a ʺ 1 ʺ and is
cleared with a write to the appropriate ʺ Timer x IRQ Clear ʺ register. Alternately,
writing a ʺ 0 ʺ to TCSR[7] will also clear the interrupt. When this bit is read as a ʺ 0 ʺ ,
the timer has not created an interrupt. When a ʺ 1 ʺ is written into this bit, a single
interrupt will be generated when the timer ʹ s ʺ IRQ Enable ʺ bit is enabled.
3.2.22 Timer 1 Value Register (0x634)
Timer 1 is not implemented on SBC622.
3.2.23 Timer 2 Value Register (0x636)
Timer 2 is not implemented on SBC622.
3.2.24 Timer 3 Value Register (0x638)
Timer 3 is a 32 ‐ bit timer that is located at offset 0x38 from base I/O address 0x600.
When this field is read, the value returned is either the current count value or the
loaded value, depending on the setting of TCSR3[3]. The current timer count
value is latched when either the offset address 0x0C or the offset address 0x08 is
read, depending on the setting of TER[4].
3.2.25 Timer 4 Value Register (0x63C)
Timer 4 is a 32 ‐ bit timer that is located at offset 0x3C from base I/O address 0x600.
When this field is read, the value returned is either the current value or the loaded
value, depending on the setting of TCSR4[3]). The current timer count value is
latched when either the offset address 0x10 or the offset address 0x08 is read,
depending on the setting of TER[4].
3.2.26 Timer 1 IRQ Clear (T1IC)
Timer 1 is not implemented on SBC622.
3.2.27 Timer 2 IRQ Clear (T2IC)
Timer 2 is not implemented on SBC622.
Table 3-14 Timer x Clock Select
Clock Rate Bit 2 Bit 1
2 MHz 0 0
1 MHz 0 1
500 KHz 1 0
250 KHz 1 1