56 SBC622 Hardware Reference Manual
3.2.16 Control Register 3 (0x622)
The
SBC622
only
implements
bit
6
of
this
register.
This
controls
the
LEDs.
3.2.17 IRQ Enable Register (0x623)
This
register
is
not
implemented
on
the
SBC622.
3.2.18 Drive Links Low Register (0x624)
This
register
is
not
implemented
on
the
SBC622.
3.2.19 Timers
The
SBC622
provides
two
32
‐
bit
timers
that
are
completely
dedicated
to
user
applications
and
are
not
required
for
any
standard
system
function.
Each
timer
is
clocked
by
independent
generators
with
selectable
rates
of
2
MHz,
1
MHz,
500
KHz
and
250
KHz.
Each
timer
may
be
independently
enabled
and
each
is
capable
of
generating
a
system
interrupt
on
timeout.
Events
can
be
timed
by
either
polling
the
timers
or
enabling
the
interrupt
capability
of
the
timer.
A
status
register
allows
for
application
software
to
determine
which
timer
is
the
cause
of
any
interrupt.
NOTE
Register definitions exist for four timers (two 16-bit and two 32-bit). The SBC622 only implements
the two 32-bit timers.
Table 3-10 Control Register 3 (0x622)
Bits Meaning
D7
BIT Pass (Green LED)
1 = LED lit
0 = LED off (default)
D6
BIT Fail (Red LED)
1 = LED lit (default)
0 = LED off
D5
BIT Status 1 (Yellow LED)
1 = LED lit
0 = LED off (default)
D4
BIT Status 0 (Yellow LED)
1 = LED lit
0 = LED off (default)
D3 and D2
RESERVED
D1 and D0
RESERVED
Содержание OpenVPX VPXcel6 SBC622
Страница 2: ...Document History Hardware Reference Document Number 500 9300527818 000 Rev B March 18 2011 ...
Страница 30: ...30 SBC622 Hardware Reference Manual Figure 1 2 SBC622 in Chassis VPX Backplane SBC622 inserted into Chassis ...
Страница 33: ...Installation and Setup 33 Figure 1 3 PMC Installed onto 2 PMC Site Model F ...
Страница 37: ...Installation and Setup 37 Figure 1 5 Front Panel SBC622 Isometric View Convection cooled F F ...
