6
GEI-100268
Table 3. Plug P2 Pin Assignments, Row C
Pin No.
Nomenclature
Definition
C1
P5
+5 digital power source
C2
XD2
Data bus (D2)
C3
XD6
Data bus (D6)
C4
XD10
Data bus (D10)
C5
XD14
Data bus (D14)
C6
XD18
Data bus (D18)
C7
XD22
Data bus (D22)
C8
DCOM
+5 digital power return (common)
C9
XD26
Data bus (D26)
C10
XD30
Data bus (D30)
C11
XA2
Address bus (A2)
C12
XA6
Address bus (A6)
C13
XA10
Address bus (A10)
C14
DCOM
+5 digital power return (common)
C15
0XRD
0 = read data from BAIA request
C16
0ACL_2
0 = route keypad to ACL
C17
CPU_CLK1
Clock
C18
DCOM
+5 digital power return (common)
C19
LDPLS3
1 = Update I/O
C20
SYNC_LAN
Synchronize LAN
C21
ACOM
±
15Vdc power return (common)
C22
HIFI_1B
Hi-Fidelity input, 1 pair
C23
HIFI_3A
Hi-Fidelity input, 3 pair
C24
DCOM
+5 digital power return (common)
C25
CLK20_1
20 MHz global clock (supplied by DSPX board)
C26
T_TX_ACL
Keyboard TTL level RS232 signals to/from ACL_ board
C27
GR_1RX
ISBus (1, 2) TTL level signals to/from DSPX board
C28
GR_ACL_TX
ISBus 1 TTL level signals to/from DSPX board
C29
T_TX_TTL
Tool TTL level RS232 signals to/from DSPX board
C30
K_RTS_TTL
Keyboard TTL level RS232 signals to/from DSPX board
C31
K_RTS_ACL
Keyboard TTL level RS232 signals to/from ACL_ board
C32
P5
+5 digital power source