Fujitsu MB89950 Series, Руководство по оборудованию

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CHAPTER 6 WATCHDOG TIMER
6.1 Overview of Watchdog Timer
The watchdog timer is a 2-bit counter that uses, as its count clock source, the timebase
timer derived from the main clock. The watchdog timer resets the CPU if not cleared
within a fixed time after activation.
■
Watchdog timer function
The watchdog timer is a counter provided to guard against program runaway. Once activated, the counter
must be repeatedly cleared within a fixed time interval. If the program becomes trapped in an endless loop
or similar and does not clear the counter within the fixed time, the watchdog timer generates a four-
instruction cycle watchdog reset to the CPU.
The timebase timer output can be selected as the watchdog timer count clock.
Table 6.1-1 "Watchdog timer interval time" lists the watchdog timer interval times. If not cleared, the
watchdog timer generates a watchdog reset at a time between the minimum and maximum times listed.
Clear the counter within the minimum time given in the table.
See Section 6.4, "Operation of Watchdog Timer" for the details on the minimum and maximum time of the
watchdog timer interval times.
Reference:
The watchdog timer counter is cleared whenever the device goes to sleep or stop mode. Operation halts
until the device returns to normal operation (RUN state).
Table 6.1-1 Watchdog timer interval time
Count clock
Timebase timer output
(main clock oscillation frequency at 5 MHz)
Minimum time
Approx. 419.43 ms
(*1)
Maximum time Approx. 838.86 ms
*1: Divide-by-two of the main clock oscillation frequency (F
CH
) x timebase timer count value (2
20
).