iii
MB86R12 Application Note
DDR3 Interface PCB
Design Guideline
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Contents
1.
Floor plan ............................................................................................................ 1
2.
PCB laminating ................................................................................................... 2
3.
DDR3_SDRAM specifications ............................................................................ 3
4.
Signal design restrictions (DDR3 interface part) ............................................. 4
4.1.
Definition of signal line group ................................................................................................................ 4
4.2.
General wiring restrictions ...................................................................................................................... 5
4.3.
Resistance ................................................................................................................................................ 5
4.4.
Terminal resistance/Damping resistance/Wire length ............................................................................. 6
4.5.
Wiring gap/Crosstalk ............................................................................................................................... 7
4.6.
ZQ/ODT setting ...................................................................................................................................... 8
4.7.
Wiring topology ...................................................................................................................................... 9
4.7.1.
Wiring topology diagram of MCK_Group ...................................................................................... 9
4.7.2.
Wiring topology diagram of MDQSx_Group................................................................................ 10
4.7.3.
Wiring topology diagram of MDQx_Group ................................................................................... 11
4.7.4.
Wiring topology diagram of MCNTL_Group/MCMD_Group ..................................................... 12
5.
Power system design restrictions .................................................................. 13
5.1.
Number and capacity of bypass capacitor ............................................................................................. 13
5.2.
Pull-out wiring condition ...................................................................................................................... 14