Fujitsu F2MC-16LX Series, Руководство по оборудованию, Страница: 513 / 710

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CHAPTER 16 CAN controller
16.3.5 Bit timing register (BTR)
The bit timing register (BTR) sets the prescaler and bit timing.Set this after halting the
bus (CSR: HALT = 1).
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Bit timing register (BTR)
Figure 16.3-9 Bit timing register (BTR)
bit15
Reset value
X 1 1 1 1 1 1 1
B
TS2.2 TS2.1 TS2.0 TS1.3 TS1.2 TS1.1 TS1.0
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
R/W
7
R/W
RSJ1
Reset value
1 1 1 1 1 1 1 1
B
RSJ0 PSC5 PSC4 PSC3 PSC2 PSC1 PSC0
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
: Unused
X : Undefined
R/W : Read/Write
Table 16.3-7 Function of bit timing register (BTR)
Bit name Function
bit0
to
bit5 PSC5 to 0:
prescaler setting bit 5
to 0 These bits divide the frequency of the system clock to
determine the time quantum (TQ) of the CAN controller.
bit6,
bit7 RSJ1 to 0:
resynchronous jump
width setting bits 1, 0 These bits set the resynchronous jump width (RSJW).
bit8
to
bit11 TS1.3 to 1.0:
time segment 1 setting
bits 3 to 0 These bits set the time of time segment 1 (TSEG1).
Time segment 1 is equivalent to propagation segment
(PROP_EG) and phase buffer segment 1 (PHASE_SEG1)
based on CAN specifications.
bit12
to
bit14 TS2.2 to 2.0:
time segment 2 setting
bits 2 to 0 These bits set the time of time segment 2 (TSEG2).
Time segment 2 is equivalent to phase buffer segment 2
(PHASE_SEG2) based on CAN specifications.
Note:
Set the bit timing register (BTR) after halting the bus (CSR: HALT = 1). After setting the bit timing
register (BTR), write 0 to the HALT bit in the control status register to cancel the bus halt.