MT5F33743
4. Operation Condition and Dead Time Setting
© Fuji Electric Co., Ltd. All rights reserved.
Since principal characteristics of IGBT depend on driving conditions like
V
GE
and
R
G
, certain setting
according to target design is needed. Gate bias condition and dead time setting are described here.
4.1 Forward bias voltage : +
V
GE
(on state)
Notes when +
V
GE
is designed are shown as follows.
(1) Set +
V
GE
so that is remains under the maximum rated G-E voltage,
V
GES
=
±
20V.
(2) It is recommended that supply voltage fluctuations are kept to within
±
10%.
(3) The on-state C-E saturation voltage
V
CE(sat)
is inversely dependent on +
V
GE
, so the greater the
+
V
GE
the smaller the
V
CE(sat)
.
(4) Turn-on switching time and switching loss grow smaller as +
V
GE
rises.
(5) At turn-on (at FWD reverse recovery), the higher the +
V
GE
the greater the likelihood of surge
voltages in opposing arms.
(6) Even while the IGBT is in the off-state, there may be malfunctions caused by the d
v
/d
t
of the
FWD’s reverse recovery and a pulse collector current may cause unnecessary heat generation.
This phenomenon is called a d
v
/d
t
shoot through and becomes more likely to occur as +
V
GE
rises.
(7) The greater the +
V
GE
the smaller the short circuit withstand capability.
4.2 Reverse bias voltage : -
V
GE
(off state)
Notes when -
V
GE
is designed are shown as follows.
(1) Set -
V
GE
so that it remains under the maximum rated G-E voltage,
V
GES
=
±
20V .
(2) It is recommended that supply voltage fluctuations are kept to within
±
10%.
(3) IGBT turn-off characteristics are heavily dependent on -
V
GE
, especially when the collector current
is just beginning to switch off. Consequently, the greater the -
V
GE
the shorter, the switching time
and the switching loss become smaller.
(4) If the -
V
GE
is too small, d
v
/d
t
shoot through currents may occur, so at least set it to a value
greater than -5V. If the gate wiring is long, then it is especially important to pay attention to this.
5-7
Fig. 5-9 Principle of unexpected turn-on
In this section, the way to avoid the unexpected
IGBT turn-on by d
v
/d
t
at the FWD’s reverse recovery
will be described.
Fig. 5-9 shows the principle of unexpected turn-on
caused by d
v
/d
t
at reverse recovery. In this figure, it
is assumed that IGBT
1
is turned off to on and gate to
emitter voltage
V
GE
of IGBT
2
is negative biased. In
this condition, when IGBT
1
get turned on from
off-state, FWD on its opposite arm, that is, reverse
recovery of FWD
2
is occurred. At same time, voltage
of IGBT
2
and FWD
2
with off-state is raised. This
causes the d
v
/d
t
according to switching time of
IGBT
1
. Because IGBT
1
and IGBT
2
have the mirror
capacitance
C
res
, Current is generated by d
v
/d
t
through
C
res
. This current is expressed by
C
res
x
d
v
/d
t
. This current is flowed through the gate resistance
R
G
, results in increasing the gate potential.
4.3 Avoid the unexpected turn-on by recovery d
v
/d
t
IGBT
1
IGBT
2
FWD
2
FWD
1
R
G
R
G
Off state
i
=
C
res
×
d
v/
d
t
