BIOS Configuration
Chipset Features Setup
39
4.4. Chipset Features Setup
Selecting “Chipset Features Setup” on the main program screen dis-
plays this menu:
CMOS Setup Utility – Copyright (C) 1984 – 2000 Award Software
Advanced Chipset Features
Item Help
DRAM Timing by SPD
Disabled
SDRAM Cycle Length
3
Bank Interleave
Disabled
DRAM Clock
Host CLK
Memory Hole
Disabled
PCI Master Pipeline Req
Enabled
P2C/C2P Concurrency
Enabled
Fast R-W Turn Around
Disabled
System BIOS Cacheable
Enabled
Video RAM Cacheable
Enabled
AGP Aperture Size
64M
AGP-4x Mode
Enabled
AGP Driving Control
Auto
X AGP Driving Value
DA
K7 CLK_CTL Select
Optimal
OnChip USB
Enabled
USB Keyboard Support
Disabled
OnChip Sound
Auto
Menu Level
↑
↑
↓
↓
→
→
←
←
: MoveEnter : Select +/-/PU/PD:Value: F10: Save ESC: Exit F1:General Help
F5:Previous Values
F6:Fail-Safe Defaults
F7:Optimized Defaults
Figure 4-4:
Chipset features setup
This screen controls the settings for the board’s chipset. All entries related
to the DRAM timing on the screen are automatically configured. Do not
make any changes unless you are familiar with the chipset.
DRAM Timing by SPD:
Enable this item if you want the system
SPD (Serial Presence Detect) to automatically detect the speed of the
installed memory modules.
SDRAM Cycle Length:
This field enables you to set the CAS la-
tency time in HCLKs of 2/2 or 3/3. The system board designer
should have set the values in this field, depending on the DRAM in-
stalled. Do not change the values in this field unless you change
specifications of the installed DRAM or the installed CPU.
Bank Interleave:
Enable this item to increase memory speed. When
enabled, separate memory banks are set for odd and even addresses
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