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P5F97/P5F103 User’s Manual
M1541:
- CPU interface controller
- AGP Interface controller
- Integrated DRAM/Cache controller
- Extensive CPU-to-AGP, CPU-to-DRAM,
CPU-to-PCI, AGP-to-DRAM, AGP-to-
PCI, PCI-to-AGP and PCI-to-DRAM data
buffering
M1543:
- Interface between the PCI and ISA buses
- Fully synchronous PCI 2.1 bus interface
- Power Management Logic
- USB controller
- EIDE controller
- Seven DMA channels, one timer/counter,
two eight-channel interrupt controllers,
NMI logic, SMI interrupt logic, and PCI/
ISA bus arbitrator
- SMBus interface
- Real-Time clock
- Super I/O and Keyboard controller
1.7 Main Memory
The P5F97/P5F103 mainboard provides three 168-pin DIMM
sockets to support 8MB to 768MB of system memory. The sockets
support 1M x 64 (8MB), 2M x 64 (16MB), 4M x 64 (32MB), 8M x
64 (64MB), 16Mx64(128MB) and 32Mx64(256MB) DIMM in
single- or double-sided modules. The DIMM have to be 3.3V &
unbuffered memory.
The P5F97/P5F103 supports two types of DRAMs, Extended Data
Out (EDO), and Synchronous DRAM (SDRAM). Memory timing
requires 70ns or faster for EDO, and equal or faster speed than the
CPU bus clock for SDRAMs.
The P5F97/P5F103 mainboard achieves the highest reliability by
supporting the ECC (Error Checking and Correction) memory
protections. The ECC is a hardware scheme which detects all single
and dual-bit errors, and corrects all single-bit error during main
memory access. The ECC can be supported only if all the DIMM
Chapter 1: Introduction
