Freescale Semiconductor MCF5441X, Руководство пользователя

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MCF5441X Tower Module Hardware Specification Page 16 of 31
4.13.2 Parallel Configuration (J5: 3-4 and 1-2 = ON:OFF)
If the BOOTMOD pins are 01 during reset, the MCF5441x configuration after reset is determined
according to the levels driven onto the FB_AD[7:0] pins. On the TWR-MCF5441X, the FB_AD[7:0] pins
are actively driven by two 4-bit buffers enabled when the MCF5441x RSTOUT signal is asserted. The
values driven by the buffer are set by the SW1 DIP switch settings. For SW1, a value of 0 implies that
the dip is switched “On”.
Override Pins in Reset Function
SW1- DIP 1 Boot Memory
0 (Default) NAND Flash
1 FlexBus
SW1-2 PLL mode
0 Disabled
1 (Default) Enabled
SW1-3 Oscillator mode
0 (Default) Crystal oscillator mode
1 Oscillator bypass mode
SW1-4 FB_ALE select
0 FB_TS_B
1 (Default) FB_ALE
SW1-[6:5] BOOT Port size
00 32-bit (32-bit muxed address)
01 8-bit (24-bit non-muxed address)
10 (Default) 16-bit (16-bit non-muxed address)
11 16-bit (16-bit non-muxed address)
SW1-[8:7] PLL Multiplier
00 (Default) Fvco = 10 x Fref
01 Fvco = 15 x Fref
10 Fvco = 16 x Fref
11 Fvco = 20 x Fref
Table 10 - SW1 8-way DIP switch