MCF5441X Tower Module Hardware Specification
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To fully support the DDR2 interface a VCO of 500 MHz is required. In order to supply a VCO of
500MHz, the clock multiplier should be adjusted based on the input reference clock.
Clock Source
PLL Multiplier
SW1 Dip [7:8]
settings
50MHz
10x
0:0 (On:On)
25MHz
20x
1:1 (Off:Off)
Note: VCO must be in the range from 240-500 MHz. USB frequency must be 60MHz, SDHC frequency
must not be greater than 250MHz, and NAND frequency must not be greater than 80MHz.
4.3
System Power
The TWR-MCF5411X board is powered by +5V either from the OSBDM circuit (via the miniAB USB
connector) or the Tower Elevator power connections. Power regulation circuitry is capable of
providing 1.2V, 1.8V, and if needed 3.3V from either of the power source.
4.4
Debug Interface
TWR-MCF5441X provides two debug interfaces – a standard BDM and an Open Source BDM (OSBDM).
4.4.1
Stardard BDM
The primary debug port on the TWR-MCF5441
X
is referred to as the background debug module or
BDM. The standard 26-pin BDM header (J11) is provided on the TWR-M5441X for attachment of an
external BDM control interface.
