Errata for Revision 2.3
MCF5282 User’s Manual Errata, Rev. 15
Freescale Semiconductor
3
Table 10-14/Page 10-15
Change flag clearing mechanism for sources 24-26. They should read as follows:
Write ERR_INT = 1 after reading ERR_INT = 1
Write BOFF_INT = 1 after reading BOFF_INT = 1
Write WAKE_INT = 1 after reading WAKE_INT = 1
Table 12-7/Page 12-7
BAM bit field description, the first example should read “So, if CSAR0 = 0x0000 and
CSMR0[BAM] = 0x0001” instead of “So, if CSAR0 = 0x0000 and CSMR0[BAM] = 0x0008”.
Table 10-2/Page 10-4
In footnote, remove mention of the SWIACK register, as it is not supported in the global
IACK space.
Section 10.3.7/Page 10-16 Change last paragraph to: “In addition to the IACK registers within each interrupt controller,
there are global LnIACK registers. A read from one of the global LnIACK registers returns
the vector for the highest priority unmasked interrupt within a level for all interrupt
controllers. There is no global SWIACK register. However, reading the SWIACK register
from each interrupt controller returns the vector number of the highest priority unmasked
request within that controller.”
Table 15-1/Page 15-3
NOP command entry. Replace “SRAS asserted” with “SDRAM_CS[1:0] asserted”
Table 15-5/Page 15-7
Add the following note to the DACRn[CBM] field description:
Note: It is important to set CBM according to the location of the command bit.
Section 16.5/Page 16-11
Remove last sentence in this section starting with “BCRn decrements...” since SAA bit is
not supported.
Chapter 17
The maximum buffer size of the FEC is 2032 bytes. Replace any mention of the max size
being 2047 bytes with 2032 bytes.
Section 17.4.6/Page 17-7
Add the following subsection entitled “Duplicate Frame Transmission”:
The FEC fetches transmit buffer descriptors (TxBDs) and the corresponding transmit data
continuously until the transmit FIFO is full. It does not determine whether the TxBD to be
fetched is already being processed internally (as a result of a wrap). As the FEC nears the
end of the transmission of one frame, it begins to DMA the data for the next frame. In order
to remain one BD ahead of the DMA, it also fetches the TxBD for the next frame. It is
possible that the FEC will fetch from memory a BD that has already been processed but not
yet written back (that is, it is read a second time with the R bit still set). In this case, the data
is fetched and transmitted again.
Using at least three TxBDs fixes this problem for large frames, but not for small frames. To
ensure correct operation for either large or small frames, one of the following must be true:
• The FEC software driver ensures that there is always at least one TxBD with the ready
bit cleared.
• Every frame uses more than one TxBD and every TxBD but the last is written back
immediately after the data is fetched.
• The FEC software driver ensures a minimum frame size,
n
. The minimum number of
TxBDs is then (Tx FIFO Size
÷
(n + 4)) rounded up to the nearest integer (though the
result cannot be less than three). The default Tx FIFO size is 192 bytes; this size is
programmable.
Table 17-9/Page 17-17
Correct MIB block counters end addresses to 0x12FF.
Table 17-11/Page 17-19
Add RMON_R_DROP with an IPSBAR Offset of 0x1280 and a description of ‘Count of
frames not counted correctly’.
Figure 17-26/Page 17-41
Change EMRBR register address from “ 0x11B8” to “ 0x1188”.
Section 20.5.13/Page 20-12 Deleted reference to nonexistent CF bits in the figure and bit descriptions for the GPTFLG2
register.
Table 1. MCF5282UM Rev 2.3 Errata (continued)
Location
Description
