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MCF5282 User’s Manual Errata, Rev. 15

Errata for Revision 1.0

Freescale Semiconductor

J15

DTOUT1

PTD2

URTS1/

URTS0

U1/U0 Request to Send

I/O

—

J14

DTIN0

PTD1

UCTS1/

UCTS0

U1/U0 Clear to Send

I/O

—

J13

DTOUT0

PTD0

UCTS1/

UCTS0

U1/U0 Clear to Send

I/O

—

General Purpose Timers

T13:R13:P13:N13

GPTA[3:0]

PTA[3:0]

—

Timer A IC/OC/PAI

I/O

Yes

T12:R12:P12:N12

GPTB[3:0]

PTB[3:0]

—

Timer B IC/OC/PAI

I/O

Yes

N14

SIZ1

PE3

SYNCA

Timer A synchronization input

I/O

Yes

M16

SIZ0

PE2

SYNCB

Timer B synchronization input

I/O

Yes

M15

PE1

SYNCA

Timer A synchronization input

I/O

Yes

M14

TIP

PE0

SYNCB

Timer B synchronization input

I/O

Yes

DMA Timers

K16

DTIN3

PTC3

URTS1/

URTS0

Timer 3 in

I/O

—

K15

DTOUT3

PTC2

URTS1/

URTS0

Timer 3 out

I/O

—

K14

DTIN2

PTC1

UCTS1/

UCTS0

Timer 2 in

I/O

—

K13

DTOUT2

PTC0

UCTS1/

UCTS0

Timer 2 out

I/O

—

J16

DTIN1

PTD3

URTS1/

URTS0

Timer 1 in

I/O

—

J15

DTOUT1

PTD2

URTS1/

URTS0

Timer 1 out

I/O

—

J14

DTIN0

PTD1

UCTS1/

UCTS0

Timer 0 in

I/O

—

J13

DTOUT0

PTD0

UCTS1/

UCTS0

Timer 0 out

I/O

—

Queued Analog-to-Digital Converter (QADC)

AN0

PQB0

ANW

Analog channel 0

I/O

—

AN1

PQB1

ANX

Analog channel 1

I/O

—

AN2

PQB2

ANY

Analog channel 2

I/O

—

AN3

PQB3

ANZ

Analog channel 3

I/O

—

Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function (continued)

MAPBGA Pin

Pin Functions

Description

Primary

I/O

Internal

Pull-up

Primary

Secondary

Tertiary

Содержание MCF5282

Страница 1: ...MCF5282 ColdFire Microcontroller User s Manual order number MCF5282UM For convenience the addenda items are grouped by revision Please check our website at http www freescale com for the latest update...

Страница 2: ...e to NOTE Peripheral IPSBAR space should not be cached The combination of the CACR defaults and the two ACRn registers must define the non cacheable attribute for this address space Figure 5 1 Page 5...

Страница 3: ...on entitled Duplicate Frame Transmission The FEC fetches transmit buffer descriptors TxBDs and the corresponding transmit data continuously until the transmit FIFO is full It does not determine whethe...

Страница 4: ...by writing a one instead of a zero Table 26 1 Page 26 5 Change description field for DTOUT1 from DMA timer 1 output Port TD 3 to DMA timer 1 output Port TD 2 Change description field for DTIN0 from DM...

Страница 5: ...hanged to Invalidate 2 KByte instruction cache Figure 6 3 6 6 Changed bit 8 to write only instead of read write Table 6 10 6 15 Removed selected by BKSL 1 0 as these are internal signal names not nece...

Страница 6: ...it as a zero to To clear an interrupt flag first read the flag as a one then write it as a one Chapter 33 It is crucial during power up that VDD never exceeds VDDH by more that 0 3V There are diode d...

Страница 7: ...5 2 Replace the description of PRI1 and PRI2 with the following Table 5 1 5 3 Add the following note to the SPV bit description The BDE bit in the second RAMBAR register must also be set to allow dual...

Страница 8: ...allow a level 7 IRQ to generate a wakeup That is the wakeup mask value used by the interrupt controller must be in the range of 0 6 Figure 12 4 12 8 Change CSCRn to reflect that AA is set to 1 at res...

Страница 9: ...he port C and D pins and PJ 5 4 BS 1 0 can be configured as general purpose input output I O 32 2 32 7 Added additional device number order information to Table 32 2 Chapter 33 Delete references to TA...

Страница 10: ...ow Table 14 3 MCF5282 Signals and Pin Numbers Sorted by Function MAPBGA Pin Pin Functions Description Primary I O Internal Pull up 1 Primary2 Secondary Tertiary Reset R11 RSTI Reset in I Yes P11 RSTO...

Страница 11: ...B4 A4 B3 A3 A 20 16 PF 4 0 Address bus O Yes A2 B1 B2 C1 C2 C3 D1 D2 A 15 8 PG 7 0 Address bus O Yes D3 D4 E1 E2 E3 E4 F1 F2 A 7 0 PH 7 0 Address bus O Yes F3 G1 G2 G3 G4 H1 H2 H3 D 31 24 PA 7 0 Data...

Страница 12: ...4 C15 C16 D14 D15 IRQ 7 1 PNQ 7 1 External interrupt request I O Ethernet C10 EMDIO PAS5 URXD2 Management channel serial data I O B10 EMDC PAS4 UTXD2 Management channel clock I O A8 ETXCLK PEH7 MAC Tr...

Страница 13: ...U0 receive data I O T7 UTXD0 PUA0 U0 transmit data I O C10 EMDIO PAS5 URXD2 U2 receive data I O B10 EMDC PAS4 UTXD2 U2 transmit data I O D16 CANRX PAS3 URXD2 U2 receive data I O E13 CANTX PAS2 UTXD2 U...

Страница 14: ...IP PE0 SYNCB Timer B synchronization input I O Yes DMA Timers K16 DTIN3 PTC3 URTS1 URTS0 Timer 3 in I O K15 DTOUT3 PTC2 URTS1 URTS0 Timer 3 out I O K14 DTIN2 PTC1 UCTS1 UCTS0 Timer 2 in I O K13 DTOUT2...

Страница 15: ...I TDI Debug data in TAP data in I Yes7 T10 DSO TDO Debug data out TAP data out O C12 D12 A13 B13 DDATA 3 0 PDD 7 4 Debug data I O C13 A14 B14 A15 PST 3 0 PDD 3 0 Processor status data I O Test N10 TES...

Страница 16: ...umber Substantive Changes Date of Release 0 Initial release 07 2003 1 Added page erase verify errata for Chapter 6 ColdFire Flash Module CFM 09 2003 2 Added errata for UART interrupt status register A...

Страница 17: ...he 16 bit divider from a figure and equation 08 2005 12 Added core watchdog unable to reset the device errata Added EMRBR register address errata Added IOH and IOL errata 12 2005 13 Added FlexCAN flag...

Страница 18: ...particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including with...

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