Schematic
KTVR500UG Rev. 1.0 8/2014
Freescale Semiconductor, Inc.
19
Figure 15. KITVR500EVM Switching Regulators Schematic
PVIN1_1 PVIN1_2 PVIN1_3
Default:
1-2 shunt,
3-4 shunt,
5-6 shunt.
LX1
6.0A
V_SW1
PVIN2
Default:
1-2 shunt
2.4A
LX2
FB1
FB2
V_SW2
PVIN3_1
PVIN3_2
Default:
1-2 shunt,
3-4 shunt.
2.65A
LX3
FB3
V_SW3
PVIN4
Default:
1-2 shunt
2.0A
LX4
FB4
V_SW4
PVIN1_1
PVIN1_2
PVIN1_3
LX1
V_SW 1
PVIN2
LX2
V_SW 2
PVIN3_2
PVIN3_1
LX3
V_SW 3
PVIN4
LX4
V_SW 4
SWVIN
V_SW1
SWVIN
V_SW2
SWVIN
V_SW3
SWVIN
V_SW4
C25
22UF
C64
4.7uF
TP27
DNP
TP23
DNP
C61
0.1UF
C21
0.1UF
C9
22UF
C22
22UF
C30
22UF
J19
HDR 2X3
1
2
3
4
6
5
C57
0.1UF
TP19
DNP
C59
0.1UF
C47
22UF
DNP
L1
1uH
1
2
TP39
DNP
L4
1uH
1
2
C66
4.7uF
C58
4.7uF
TP20
DNP
TP24
DNP
C13
22UF
DNP
C24
22UF
C48
22UF
DNP
C36
22UF
DNP
C15
22UF
DNP
C12
22UF
C42
22UF
DNP
C14
22UF
DNP
C46
22UF
DNP
C27
22UF
DNP
C40
22UF
L2
1uH
1
2
TP25
DNP
TP33
DNP
C39
22UF
C65
0.1UF
C43
22UF
DNP
TP22
DNP
C56
4.7uF
C11
22UF
TP21
DNP
C41
22UF
TP26
DNP
TP35
DNP
J24
HDR 1X2 TH
1
2
C49
22UF
DNP
C26
22UF
DNP
C20
22UF
DNP
C23
22UF
C55
0.1UF
C60
4.7uF
L3
1UH
1
2
TP17
DNP
C45
22UF
DNP
J23
HDR 1X2 TH
1
2
C38
22UF
C1
22UF
DNP
C18
0.1UF
TP32
DNP
TP29
DNP
C44
22UF
DNP
J22
HDR 2X2
1
2
3
4
SW2
SW3
SW4
SW1
MC34VR500V1ES
U1C
PVIN1_3
12
S
G
ND1
14
FB3
38
PVIN3_2
37
LX3_2
36
DNC4
33
PVIN3_1
34
LX3_1
35
S
G
ND3
32
FB4
19
PVIN4
20
DNC6
44
DNC7
45
DNC8
46
PVIN1_1
7
LX1_1
8
PVIN1_2
10
LX1_2
9
FB1
13
LX1_3
11
DNC2
6
FB2
25
LX2
22
LX4
21
EPGN
D
57
S
G
ND2
15
DNC1
2
DNC5
42
DNC3
16
S
G
ND4
48
PVIN2_1
23
PVIN2_2
24
C19
4.7uF
C16
22UF
C28
22UF
C17
4.7uF
VR500-SWITHCING REGULATOR O/P
TERMINAL BLOCK SECTION
SW1
0.625 to 1.875 V
4.5 A (Max. Peak)
SW3
0.625 to 1.975 V ,
2.5 A (Max. Peak)
SW4
1.0 A
operates in VTT mode
provide DDR termination
at 50% of SW3
SW2
0.625 to 1.975V ,
1.0 A (Max. Peak)
V_SW1
V_SW2
V_SW3
V_SW4
J32
SUB_TB_2X1
1
2
J29
SUB_TB_2X1
1
2
J31
SUB_TB_2X1
1
2
J30
SUB_TB_2X1
1
2
VR500-SWITHCING REGULATOR O/P HDR
V_SW 1
V_SW 1
V_SW 4
V_SW 4
V_SW 2
V_SW 3
V_SW 2
V_SW 3
V_SW1
V_SW2
V_SW1
V_SW4
V_SW4
V_SW2
V_SW3
V_SW3
J35
CON_2X10
1
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PROGRAMMING INTERFACE
3V3
MCU_SDA
GPIO1
MCU_SCL
EN
GPIO2
3V3
MCU_SDA
3,5
5
1
O
I
P
G
MCU_SCL
3,5
EN
3,5
GPIO2
5
J20
HDR 2X4
1
2
3
4
6
5
7
8
C5
0.1UF
VOUT = 1.242 X ( (R2/R1) + 1) = 3.3V
R2 = ((VOUT/1.242) -1) X R1
LDO REGULATOR 3.3 V
Layout Note :
Place this LDO section
on the bottom side of the PCB.
R1
R2
VIN_USB
LD0_3V3_EN
3V3
LDO_3V3_ADJ
3V3
VIN_USB
3V3
3V3
LD0_3V3_EN
5
R21
12.0K
R22
20K
U3
MIC5205
IN
1
GND
2
ADJ
4
EN
3
OUT
5
C79
1.0UF
C71
470PF
+
C80
2.2UF
C74
2.2uF
DNP
