Freescale Semiconductor KITVR500EVM, Руководство пользователя

Страница: 17 / 27

Schematic
KTVR500UG Rev. 1.0 8/2014
Freescale Semiconductor, Inc. 17
Figure 13. Evaluation Board Schematic, Part 2
GND
PVIN
SWVIN
Default:
1-2 shunt Default:
1-2 shunt
Default:
No shunt
Supply
Input Source
PVIN -
Main Input supply to the board
Input Terminal Block J1 pin 2
SWVIN -
VR500 Swithcing Regulator input
Input Terminal Block J1 pin 3
(or)
Feed the power from PVIN
by shunting the header J6.
VIN -
VR500 Main chip supply &
Input supply for LDO.
Feed the power from PVIN
by shunting the header J7
(or)
Feed the power from SWVIN
by shunting the header J11.
SWVIN PVIN SWVIN
VIN
J6
HDR 1X2 TH
1
2
J7
HDR 1X2 TH
1
2
J11
HDR 1X2 TH
1 2
J1
SUB_TB_3X1
1
2
3
VR500 - CONTROL SIGNALS
TERMINAL BLOCK SECTION
GND
EN
STBY
POR_B
INT_B
5 , 3 N E
3 Y B T S
POR_B 3
3 B _ T N I
J4
SUB_TB_3X1
1
2
3
J5
SUB_TB_3X1
1
2
3
I2C Terminal Blocks
MCU_SCL
MCU_SDA
GND
VCCI2C
VCCI2C
MCU_SCL 3,5
MCU_SDA 3,5
J3
SUB_TB_2X1
1
2
J2
SUB_TB_2X1
1
2
R O T A C I D N I N W O D T U H S R O T A C I D N I T P U R R E T N I
INT_B
EN
INT_B
EN
PVIN PVIN
3 B _ T N I 5 , 3 N E
R2
200 OHM
Q2
FDV302P
1
3
2
D1
LED Red
A
C
Q3
FDV302P
1
3
2
D2
LED Red
A
C
R3
200 OHM
RESET INDICATOR
POR_B
POR_B
PVIN
PVIN
POR_B 3
Red Grn
D3
LED_RED-GRN
4
2 1
3
R4
200 OHM
G
D
S
G
S
D
Q1
FDC6327C
2
6
1
5
4
3
R1
200 OHM
VR500 - LDO & REFOUT O/P HEADER SECTION
V_LDO1
V_LDO2
V_LDO3
V_LDO4
V_LDO5
REFOUT
V_LDO1 V_LDO2 V_LDO3 V_LDO4 V_LDO5 REFOUT
J34
CON_2X10
1 2
3 4
6
5
7
8
9 10
11 12
13 14
15 16
17 18
19 20