Schematic
KTVR500UG Rev. 1.0 8/2014
16
Freescale Semiconductor, Inc.
5
Schematic
Figure 12. Evaluation Board Schematic, Part 1
LDO INPUT SENSE POINTS
V_LDO1
V_LDO2
V_LDO3
V_LDO4
V_LDO5
LDO OUTPUT SENSE POINTS
REFOUT
Default:
1-2 shunt
VLDOIN45
VLDOIN23
VLDOIN1
REFIN
VHALF
V_LDO1
V_LDO5
V_LDO4
V_LDO2
V_LDO3
REFOUT
VLDOIN45
VLDOIN23
VLDOIN1
REFIN
VHALF
V_LDO1
V_LDO2
V_LDO3
V_LDO4
V_LDO5
REFOUT
VIN
V_SW3
C4
2.2UF
TP40
DNP
C31
1.0UF
C35
0.1UF
TP9
DNP
TP38
DNP
C34
4.7uF
TP11
DNP
J12
HDR 1X2 TH
1
2
C62
4.7uF
TP37
DNP
TP13
DNP
TP12
DNP
C37
0.1UF
TP30
DNP
J13
HDR 1X2 TH
1
2
J14
HDR 1X2 TH
1
2
C10
2.2UF
LDO
REF
REG
MC34VR500V1ES
U1B
LDO1
18
VLDOIN45
40
VHALF
29
VLDOIN1
17
LDO5
41
REFIN
30
REFOUT
31
LDO2
26
LDO3
28
VLDOIN23
27
LDO4
39
C54
1.0UF
C29
1.0UF
R11
0
C33
1.0UF
TP36
DNP
C32
2.2UF
TP34
DNP
C63
1.0UF
TP18
DNP
VIN_SENSE
VDIG
VBG
VCC
L
C
S
A
D
S
Default:
1-2 shunt
Default:
1-2 shunt,
3-4 shunt.
POR_B
STBY
INT_B
VR500_EN
Default:
1-2 shunt
Default:
No shunt
Default:
No shunt
Default:
1-2 shunt
VIN
VCC
VBIAS
VBG
VDIG
VCCI2C
I2C_SCL
I2C_SDA
MCU_SDA
MCU_SCL
STBY
INT_B
POR_B
EN
VR500_EN
VIN
V_SW2
VCCI2C
VCCI2C
PVIN
3V3
PVIN
MCU_SCL
3,5
MCU_SDA
3,5
STBY
3
INT_B
3
POR_B
3
EN
3,5
J16
HDR 1X2 TH
1
2
SW 1
FSMSM
DNP
1
2
TP4
DNP
C8
0.47uF
TP6
DNP
TP16
DNP
R7
1M
C51
1.0UF
Control
MC34VR500V1ES
U1A
ICTEST1
5
INT
1
POR
3
SCL
54
SDA
53
STBY
4
VDIG
51
VBG
52
VCCI2C
55
ICTEST2
47
EN
56
VCC
49
VIN
50
VBIAS
43
TP10
DNP
J9
HDR 1X2 TH
1
2
TP14
DNP
J15
HDR 2X2
1
2
3
4
C3
1.0UF
DNP
TP15
DNP
TP8
DNP
R10
10.0K
R6
4.7K
R8
10.0K
R9
100K
C52
1.0UF
R5
4.7K
J10
HDR 1X2 TH
1
2
C53
0.22uF
TP7
DNP
C2
1.0UF
C7
1.0UF
J17
HDR 2X2
1
2
3
4
C6
0.1UF
TP5
DNP
TP3
DNP
J8
HDR 1X2 TH
1
2