Freescale Semiconductor *KE02 Series, Технические данные инструкция

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communicating with slower peripheral devices. All timing is shown with respect to 20%
V
DD
and 80% V
DD
, unless noted, and 25 pF load on all SPI pins. All timing assumes
high-drive strength is enabled for SPI output pins.
Table 17. SPI master mode timing
Nu
m.
Symbol Description Min. Max. Unit Comment
1 f
op
Frequency of operation f
Bus
/2048 f
Bus
/2 Hz f
Bus
is the bus
clock
2 t
SPSCK
SPSCK period 2 x t
Bus
2048 x t
Bus
ns t
Bus
= 1/f
Bus
3 t
Lead
Enable lead time 1/2 — t
SPSCK
—
4 t
Lag
Enable lag time 1/2 — t
SPSCK
—
5 t
WSPSCK
Clock (SPSCK) high or low time t
Bus
– 30 1024 x t
Bus
ns —
6 t
SU
Data setup time (inputs) 8 — ns —
7 t
HI
Data hold time (inputs) 8 — ns —
8 t
v
Data valid (after SPSCK edge) — 25 ns —
9 t
HO
Data hold time (outputs) 20 — ns —
10 t
RI
Rise time input — t
Bus
– 25 ns —
t
FI
Fall time input
11 t
RO
Rise time output — 25 ns —
t
FO
Fall time output
(OUTPUT)
2
8
6 7
MSB IN2
LSB IN
MSB OUT2 LSB OUT
9
5
5
3
(CPOL=0)
4 11
11
10
10
SPSCK
SPSCK
(CPOL=1)
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1. If configured as an output.
SS1
(OUTPUT)
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
BIT 6 . . . 1
BIT 6 . . . 1
Figure 17. SPI master mode timing (CPHA=0)
Peripheral operating requirements and behaviors
KE02 Sub-Family Data Sheet, Rev4, 10/2014.
28 Freescale Semiconductor, Inc.