Freescale Semiconductor *KE02 Series, Технические данные инструкция

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1. Typical values are based on characterization data at V
DD
= 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a RESET pin request.
3. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
4. Timing is shown with respect to 20% V
DD
and 80% V
DD
levels. Temperature range -40 °C to 105 °C.






 
t
extrst
RESET_b pin
Figure 9. Reset timing
t
IHIL
KBIPx
t
ILIH
IRQ/KBIPx
Figure 10. KBIPx timing
5.2.2 FTM module timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the
fastest clock that can be used as the optional external source to the timer counter. These
synchronizers operate from the current bus rate clock.
Table 8. FTM input timing
C Function Symbol Min Max Unit
D External clock
frequency
f
TCLK
0 f
Bus
/4 Hz
D External clock
period
t
TCLK
4 — t
cyc
D External clock high
time
t
clkh
1.5 — t
cyc
D External clock low
time
t
clkl
1.5 — t
cyc
D Input capture pulse
width
t
ICPW
1.5 — t
cyc






 
t
TCLK
t
clkh
t
clkl
TCLK
Figure 11. Timer external clock
Switching specifications
KE02 Sub-Family Data Sheet, Rev4, 10/2014.
Freescale Semiconductor, Inc. 17