FS453/4 AND FS455/6
DATA SHEET: HARDWARE REFERENCE
is used to achieve the finest clock resolution, using a dithered clock. In PLL mode, the NCO is bypassed
and the clock is not dithered. The NCO can be used when HTOTAL and VTOTAL values have additional
constraints that prevent selection of values that are factors of the TV pixel rate.
2.12 Serial Control Interface
The FS453 registers are accessed through a serial input/output bus (SIO) which is I
2
C
*
-compatible and
SMBus-compatible. These registers can be read or written at any time the part is receiving a reference
clock at XTAL_IN and not being held in reset via the RESET_L pin.
2.13 Sync Timing Generator
The Sync Timing Generator provides/accepts HSync, VSync, Field and Blank signals to/from the graphics
controller.
2.14 Input Synchronization
The FS453 can operate in pseudo-master mode or slave mode. In pseudo-master mode, the GCC
derives the VGA pixel clock, horizontal sync, and vertical sync from CLKOUT supplied by the FS453. In
slave mode, the GCC generates the pixel clock, syncs and data, and the FS453 must be programmed to
generate the same pixel clock, using a common reference. Use the slave mode when the GCC does not
have a pixel clock input.
JANUARY, 2005, VERSION 3.0
8
COPYRIGHT
©
2003-4 FOCUS ENHANCEMENTS, INC.
FOCUS Enhancements Semiconductor
*
Note: I
2
C is a registered trademark of Philips Corporation. The FS453 Serial I/O bus is similar but not identical to the Philips I
2
C
bus.
