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FS453/4 AND FS455/6

DATA SHEET: HARDWARE REFERENCE

5.1 FS453

⇔

GCC Pin Mapping

Table 3 below maps the FS453 pins to the host GCC controller chip.

FBGA
Pin #

PQFP
Pin #

FS453
Pin Name

AMD
Alchemy
Pin Name

Freescale
Dragonball
Pin Name

Intel DVO
Pin Name

Intel
XScale
Pin
Name

VIA
Pin
Name

D13 56

CLKOUT GPIO

EXTAL16M TVCLKIN

TVCLK

E13 54

CLKIN_P LCD_PCLK

LSCLK

CLKOUT0 L_PCLK

TVCLKR

G12

CLKIN_N

CLKOUT1

N9 35

HSYNC

LCD_LCLK LP_HSYNC

TVHSYNC L_LCLK

TVHS

M10 36

VSYNC

LCD_FCLK FLM_VSYNC

TVVSYNC

L_FCLK

TVVS

M11 38

BLANK

LCD_BIAS

BLANK

D2 5

LCD_D16

LTVDATA0

TVDAT0

E1 6

LCD_D17

LTVDATA1

TVDAT1

E2 7

LCD_D18

LTVDATA2

TVDAT2

F1 8

LCD_D19

LD12

LTVDATA3

LDD_11 TVDAT3

F2 9

LCD_D20

LD13

LTVDATA4

LDD_12 TVDAT4

G1 10

LCD_D21

LD14

LTVDATA5

LDD_13 TVDAT5

G2 11

LCD_D22

LD15

LTVDATA6

LDD_14 TVDAT6

H1 12

LCD_D23

LD16

LTVDATA7

LDD_15 TVDAT7

H2 13

LCD_D8

LTVDATA8

TVDAT8

J1 14

LCD_D9

LTVDATA9

TVDAT9

J2 15

P10

LCD_D10

LD6

LTVDATA10

LDD_5

TVDAT10

K1 16

P11

LCD_D11

LD7

LTVDATA11

LDD_6

TVDAT11

K2 17

P12/

V656_0

(a)

LCD_D12

LD8

LDD_7

L1 18

P13/

V656_1

LCD_D13

LD9

LDD_8

N3 23

P14/

V656_2

LCD_D14

LD10

LDD_9

M4 24

P15/

V656_3

LCD_D15

LD11

LDD_10

N4 25

P16/

V656_4

LCD_D0

M5 26

P17/

V656_5

LCD_D1

N5 27

P18/

V656_6

LCD_D2

M6 28

P19/

V656_7

LCD_D3

LD0

LDD_0

N6 29

P20

LCD_D4

LD1

LDD_1

M8 32

P21/V656_H

LCD_D5

LD2

LDD_2

N8 33

P22/V656_V

LCD_D6

LD3

LDD_3

M9 34

P23/V656_F

LCD_D7

LD4

LDD_4

K12 45

SCLK

GPIO

SCL

LTVCL

SCL SPCLK1

K13 44

SDATA

GPIO

SDA

LTVDA

SDA SPD1

Table 3: FS453 to GCC Pin Mapping

(a)

Used for ITU-R BT.656 Video output

JANUARY, 2005, VERSION 3.0

COPYRIGHT

2003-4 FOCUS ENHANCEMENTS, INC.

FOCUS Enhancements Semiconductor

Содержание FS453

Страница 1: ...453 4 and FS455 6 applications This section now includes PCB Layout Guide The FS453 4 and FS455 6 Software Firmware Reference is for programmers It provides information on programming the FS453 4 and...

Страница 2: ...28 8 2 88 Lead FBGA Package 29 9 Component Placement 30 9 1 Power Ground 30 9 1 1 Power 30 9 1 2 Ground 31 9 2 DIGITAL SIGNALS 31 9 2 1 Digital Signal Routing 31 9 2 2 Video Inputs 32 9 3 ANALOG SIGN...

Страница 3: ...nts lists the pin names and maps their correspondence to sample host graphics controller chips Describes pin functions Begins on page 14 6 Control Register Function Map lists the Control Register func...

Страница 4: ...ely increase or decrease the number of video lines and pixels per line to correspond to the specific SDTV standard This allows the FS453 to precisely fill the user s television screen without adding a...

Страница 5: ...nt Oscillators and PLL Serial Control Interface Sync Timing Generator P 23 0 Demux Encoder Inverse Color Space 10 bit 10 bit 10 bit DAC A Multiplexer Sync Timing Generator VSync HSync Blank Field Colo...

Страница 6: ...th SDTV and HDTV color space matrices 2 3 Patented 2D Scaler The Patented 2D Scaler receives data from the Color Space Converter It performs vertical up or down scaling based on the value programmed i...

Страница 7: ...minance luminance and timing information into broadcast quality NTSC or PAL composite and YC S Video signals and sends them to the DACs The Inverse Color Space transforms YCrCb video data to the RGB c...

Страница 8: ...SET_L pin 2 13 Sync Timing Generator The Sync Timing Generator provides accepts HSync VSync Field and Blank signals to from the graphics controller 2 14 Input Synchronization The FS453 can operate in...

Страница 9: ...ital video data by adding artifacts Examples of artifacts are the introduction of repeated pixels the complete loss of pixel data and the creation of new pixel colors that are not interpolations of or...

Страница 10: ...are reduced to grays Detailed areas of video such as the gap in the letter e lose their distinction 3 2 1 Flicker Filter Challenges The goal is to completely remove flicker from the image without blu...

Страница 11: ...ood to 5Hz and horizontal lock with zero SC H phase The encoder must use a low jitter crystal 50 ppm to drive DAC output directly The DACs should have 10 bits of resolution and exhibit good differenti...

Страница 12: ...n though the output is interlaced because interlacing is done after vertical scaling G C C _V A C T IV E G C C _V T O T A L T V _V A C T IV E T V _V T O T A L For downscaling V SC T V _V T O T A L G C...

Страница 13: ...The image must be scaled down horizontally so HDSC is 208 D0h and HSC 00D0h For a case where input VGA width is 640 and the desired TV pixel count is 720 the image must be scaled up HUSC is 32 20h an...

Страница 14: ...19 V656_7 48 ALT_ADDR 68 DAC_A 9 P4 29 P20 49 PREF 69 VDD_DA 10 P5 30 VDD_33 50 GPIO0 70 DAC_B 11 P6 31 VSS_33 51 CLKIN_N 71 VDD_DA 12 P7 32 P21 V656_H 52 GPIO1 72 DAC_C 13 P8 33 P22 V656_V 53 RESET_L...

Страница 15: ...L P4 P3 G13 G12 G2 G1 GPIO0 CLKIN_N P6 P5 H13 H12 H2 H1 ALT_ADDR PREF P8 P7 J13 J12 J2 J1 VDD_33 VDD_18 P10 P9 K13 K12 K2 K1 SDATA SCLK P12 V656_0 P11 L13 L12 L2 L1 VSS_33 VSS_18 VDD_33 P13 V656_1 M13...

Страница 16: ...G1 10 P5 LCD_D21 LD14 LTVDATA5 LDD_13 TVDAT5 G2 11 P6 LCD_D22 LD15 LTVDATA6 LDD_14 TVDAT6 H1 12 P7 LCD_D23 LD16 LTVDATA7 LDD_15 TVDAT7 H2 13 P8 LCD_D8 LTVDATA8 TVDAT8 J1 14 P9 LCD_D9 LTVDATA9 TVDAT9 J...

Страница 17: ...al state machines and initializes default register values RSVD0 N11 39 TTL input internal pull down Reserved Manufacturing Test Pin Tie to VSS GPIO3 GPIO0 C1 C2 F1 3 G13 2 3 52 50 TTL input output Gen...

Страница 18: ...nts Semiconductor Pin Name FBGA Pin Number PQFP Pin Number Type Value Pin Function Description BLANK M11 38 GTL TTL input Digital BLANK VGA input True outside of GCC active area Connects to GCC blank...

Страница 19: ...Use 549 for a 37 5 load common or 1 1k for a 75 load Note that there is a 75 Ohm terminating resistor in consumer televisions COMP B4 75 0 1 F Compensation A 0 1 F capacitor must be connected between...

Страница 20: ...tal Power 1 8V 1 8 volt power for digital section of chip VDD_DAD B2 1 3 3 V D A Converter Digital Power VDD_DA B5 B6 B7 B8 67 69 71 73 3 3 V D A Converter Power Filtered 3 3 volt power for 10 bit vid...

Страница 21: ...onversion matrix settings QPR The Quick Program Register for rapid programming of the entire FS453 General Function Name Offset Default Value SDTV Input IHO 00h 0000h SDTV Input IVO 02h 0000h SDTV Inp...

Страница 22: ...put CR_GAIN 62h 89h SDTV Output TINT 65h 00h SDTV Output BR_WAY 69h 16h SDTV Output FR_PORCH 6Ch 20h SDTV Output NUM_PIXELS 71h 00B4h SDTV Output 1ST_LINE 73h 15h SDTV Output MISC_74 74h 02h SDTV Outp...

Страница 23: ...Color Matrix BLU_SCL ACh 0000h SDTV Output CLOSED CAPTION FIELD 1 AEh 0000h SDTV Output CLOSED CAPTION FIELD 2 B0h 0000h SDTV Output CLOSED CAPTION CONTROL B2h 0000h SDTV Output CLOSED CAPTION BLANKI...

Страница 24: ...DA VDD DA 0 3 V Forced current c d 10 0 10 0 mA Digital Outputs 3 3 V logic applied voltage Measured to VSS_33 b 0 3 0 VDD 33 VDD 33 0 3 V 5V Tolerant TTL logic applied voltage 0 3 3 0 3 6 3 8 V Force...

Страница 25: ...L Output Voltage LOW IOL 4mA 0 4 V Scalable GTL Inputs and Outputs CI I O Capacitance 4 8 pF IIH Input Current HIGH VDD 33 3 3 0 3V VIN max 10 A IIL Input Current LOW VDD 33 3 3 0 3V VIN 0 V 10 A VIH...

Страница 26: ...put Current Logic LOW 4 0 mA VOH 1 8V Output Voltage HIGH IOH 4mA 1 2 V VOL 1 8V Output Voltage LOW IOL 4mA 0 40 V IOH 1 5V Output Current Logic HIGH 4 0 mA IOL 1 5V Output Current Logic LOW 4 0 mA VO...

Страница 27: ...el Input Port tPDH Pixel Clock 0 to Data Control Hold Time VREF 0 75V 1 5V signaling 0 ns tPDH Pixel Clock 1 to Data Control Hold Time VREF 0 75V 1 5V signaling 0 ns tPSU Pixel Clock 0 to Data Control...

Страница 28: ...1 10 14 00 e BASIC 65 L 15 10 88 b 05 30 0 7 ddd 12 NOM ccc MAX 10 Notes 1 All dimensions in millimeters 2 Dimensions shown are nominal with tolerances as indicated 3 Foot length L is measured at gage...

Страница 29: ...ND FS455 6 DATA SHEET HARDWARE REFERENCE 8 2 88 Lead FBGA Package Figure 10 FBGA Package Outline Dimensions JANUARY 2005 VERSION 3 0 29 COPYRIGHT 2003 4 FOCUS ENHANCEMENTS INC FOCUS Enhancements Semic...

Страница 30: ...d reduce EMI radiation Within the FS453 separate power is routed to each functional section of the die including the phase locked loops D A converters digital processors and digital drivers Segregate...

Страница 31: ...ines is recommended in those situations A single regulator can be used for both VDD_PA and VDD_DA lines provided that those lines each have their own passive filter networks see Figure 11 above Placin...

Страница 32: ...ce the analog video output impedance cable impedance and load impedance should be matched This will reduce signal transmission reflection The output DACs of the FS453 may be configured for many differ...

Страница 33: ...ut Filter Network Figure 12 below shows the suggested output filter network for the FS453 Note that SDTV and HDTV use different values Figure 12 Recommended Output Filter JANUARY 2005 VERSION 3 0 33 C...

Страница 34: ...al will challenge the subcarrier tracking capability of the destination receiver This may range from a few ppm for broadcast equipment to a few hundred ppm for consumer equipment Crystal based clock s...

Страница 35: ...culator that can help define the characteristic impedance of a trace on a PCB Maximum power transfer and minimum reflection occur when the load resistor equals the trace impedance Also be careful to p...

Страница 36: ...OUT CLK IN SYNC DATA 9 4 3 2 Slave Mode In Slave Mode shown below the FS453 is under the complete control of the GCC The GCC provides the FS453 with all of the signals needed to produce an analog vid...

Страница 37: ...le topology and simply add the ferrite in series with the inductor Ferrite and shunt capacitor placement is critical If they are not both right on the pin HF will escape one way or another 3 Use a nea...

Страница 38: ...3sec 20 60sec Over 200 C 3 C sec Max 140 160 C 60 120sec 3 C sec Max Max 240 C Cooling down F Re flow peak E Maintain D Heat up C Pre heat B Heat up A Peak Temp IR Re flow Profile for Pre conditioning...

Страница 39: ...rption Condition 30 Moisture Absorption Condition 30 C 60 RH 192hrs C 60 RH 192hrs IR sequence Bake IR sequence Bake Absorption Absorption IR 3 times IR 3 times IR Re flow Profile Moisture Absorption...

Страница 40: ...al Highlights and Scaling and Positioning Notes Physical Layout Reference combined with Hardware Reference March 7 2003 Release V2 1 Misc minor edits Replace and corrected part numbers Noted incorpora...

Страница 41: ...e best of FOCUS knowledge but not all specifications have been characterized or tested at the time of the release of this document Parameters will be updated as soon as possible and updates made avail...

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