FLY SP-770, Как в инструкции

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PCS1900 bands over extreme temperature conditions. Inside the chip, the VCO
differential output signals are fed into the output buffer, the OPLL input feedback
buffer, and the calibration circuit. The off chip signal is transformed into a single ended
output which needs impedance matching to 50Ωto drive the power amplifier. Like RF
VCO, the oscillation bandwidth is partitioned into 128 (or 64) sub-bands for DCS/ PCS
TX VCO to cover the process and temperature variation. Calibration process begins
after a period of programmable time when the on chip TX VCO regulator is turned on.
Total calibration time needs about 60us maximally and the frequency error after
calibration is /-5 MHz. For Vtune=1.2 V, the variation of kvco is about 14%
and 40% for GSM and DCS/PCS TX VCO, respectively, across the desired frequency
range.
1.2.4 Frequency Synthesizer
1.2.4.1 Synthesizer System Description
The MT6120 includes a frequency synthesizer with a fully integrated RF VCO to
generate RX and TX local oscillator frequencies. The PLL locks the RF VCO to a
precision reference frequency at 26 MHz. In order to reduce the inherent spur caused
by fractional-N synthesizers, a 3rd-order sigma-delta modulator with dithering
function is used to generate the prescaler divider number N. The prescaler is based
on a multi-modulus architecture with programmable divider numbers ranging from 64
to 127. A conventional digital-type PFD with a charge pump is used for phase
comparison in the PLL. By changing the output current of the charge pump, the phase
detector gain can be programmed from75/π µA/rad to 600/π µA/rad.
To reduce the acquisition time or to enable fast settling time for multi-slot data
services such as GPRS, a digital loop (calibration loop) along with a fast-acquisition
system are implemented in the synthesizer. Once the synthesizer is programmed, the
RF VCO is pre-set to the vicinity of the desired frequency by a digital calibration loop.
After the calibration, a fast-acquisition system is utilized for a period of time to
facilitate fast locking. Once the acquisition is done, the PLL reverts back to the normal
operation mode.
1.2.4.2 Synthesizer Frequency Programming for RX Mode
The frequency ranges of the synthesizer for RX mode are
RX mode GSM 850 1737 MHz ~ 1788 MHz
DCS 1800 1805 MHz ~ 1880 MHz
PCS 1900 1930 MHz ~ 1990 MHz.
And the divider number N can be decided by the following procedure.
1. Calculate LO frequency fVCO from RX channel frequency fCH
fVCO = 2 * fCH – 200k for GSM 850 and E-GSM 900
fVCO = fCH – 100k for DCS 1800 and PCS 1900
2. Calculate Nint and Nfrac
N = 64 + Nint + Nfrac/5200 = fVCO/26M Nint and Nfrac are integers
0 ≤ Nfrac < 5200
3. Use the binary equivalents of Nint and Nfrac to program registers CW1-N_INT
and CW1-N_FRA.