FLI R
ADK
Ge tt in g S ta rt ed
The information contained herein does not contain technology as
defined by EAR,15 CFR772, is publicly available, and therefore
not subject to EAR.
9
3)
Turn on high immunity mode (HIM), configure HV_SRC on deserializer:
des: write val 0xE8 to reg 0xB06
4)
Turn on CLINK on serializer side (forward channel enabled)
ser: write val 0x43 to reg 0x404
5)
Turn off deserializer local I2C ACK (because we don’t need i
t anymore because forward
channel from serializer is now working)
des: write val 0x0 to reg 0xB0D
6)
Turn on Parallel video mode on serializer (may be different for MIPI) (configures forward
channel to be run from Boson’s PCLK)
ser: write val 0xF7 to reg 0x07
7)
Switch from CLINK mode to SEREN mode on serializer
(Now running off Boson’s PCLK)
ser: write val 0x83 to reg 0x404
8)
Change from GMSL1 to GMSL2 mode on serializer (we lose communication to the serializer
after doing this until deserializer is converted to GMSL2 as well) (upgrade remote side first)
ser: write val 0x91 to reg 0x06
9)
Change from GMSL1 to GMSL2 mode on deserializer (LOCK will be indicated after the link
comes back up)
des: write val 0xDF to reg 0x06
Note: The GMSL 2 configuration on serializer will be lost on power cycle, if running a GMSL
1 camera in a GMSL 2 configuration you need to implement this process each time.
4.3
GMSL SerDes Data Transmission
The Boson core of the ADK is wired to the Maxim Serializer as shown in Table 2.
Table 2: The Boson and Maxim 9295A pin correlation.
Boson
MAX9295A
Data bit 0
D2P, Pin 19
Data bit 1
D2N, Pin 20
Data bit 2
MFP5, Pin 21
Data bit 3
MFP6, Pin 22
Data bit 4
D3P, Pin 23
Data bit 5
D3N, Pin 24
Data bit 6
D0P, Pin 25
Data bit 7
D0N, Pin 26
Vsync
MFP3, Pin 17
Hsync
MFP4, Pin 18
PCLK
MFP0, Pin 2
External
Sync
MFP7, Pin 31
