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FIBOCOM NL668-AM Hardware User Manual
Page 30 of 62
Note:
RESET is a sensitive signal, so it is recommended to add an avoid debouncing capacitor close
to the module. In case of PCB layout, the RESET signal lines should keep away from the RF
interference and protected by Ground. Also, the RESET signal lines shall neither near the PCB
edge nor route on the surface planes( avoid module reset caused by ESD problems).
3.4 USB Interface
The NL668-AM module supports USB2.0 and is compatible with USB High-Speed (480Mbits/s) and USB
Full-Speed (12Mbits/s). Refer to “Universal Serial Bus Specification 2.0” for the timing and electrical
characteristics of the NL668-AM module USB bus.
3.4.1 USB interface definition
Pin name
I/O
Pin
Description
USB_DM
I/O
70
USB differential data bus ( D+ )
USB_DP
I/O
69
USB differential data bus ( D- )
USB_VBUS
PI
71
USB_DET
Table 3-9 USB Interface Definition
At present, USB just support USB_VBUS detect.
For more information about the USB 2.0 specification, please refer to http://www.usb.org/home
Note:
Since the module supports USB 2.0 High-Speed, TVS tube equivalent capacitance on the
USB_DM/DP differential signal cable is required to be less than 1pF, and a 0.5pF capacitance
TVS is recommended.
Connect a 0 ohm resistor to USB_DM / DP differential line to help analyze problems.
USB_DM and USB_DP are high-speed differential signal cables, can achieve the maximum
transmission rate of 480Mbits/s, and must follow the rules below in PCB Layout:
USB_DM and USB_DP signal cable’s control differential impedance is 90 ohm
USB_DM and USB_DP signal cables shall be parallel and equal in length, and avoid the
right-angle route;
USB_DM and USB_DP signal cables are routed on the signal layer closest to the ground layer,
and the cables shall be grounded;
