CPC1001
C P C 1 0 0 1 U s e r M a n u a l
21
© 2 0 2 1 F a s t w e l V e r . 0 0 1
1.6.3 Compliance of the SMARC interfaces and interface controllers of i.MX6
For reference, Table 1.2 shows the compliance of the SMARC interfaces and interface controllers
of the i.MX6 processor in CPC1001.
Table 1.2
– Compliance of the SMARC interfaces and i.MX6 processor
SMARC
i.MX6
Devices on CPC1001
I2C_HDMI
I2C2
-
I2C_LCD
I2C3
-
I2C_CAM
I2C2
RTC PCF8523TK, address 0xD0, (only in version CPC1001-01)
I2C_PM
I2C1
EEPROM AT24C32D, address 0xA0
I2C_GP
I2C3
-
SPI0
ECSPI1
EEPROM AT45DB321E,
EIM_EB2 ALT1 ECSPI1_SS0 or ALT5 GPIO2_IO30
SPI1
ECSPI2
-
I2S0
AUD3
-
I2S1
AUD5
-
SER0
UART3
-
SER1
UART1
-
SER2
UART2
-
CAN0
FLEXCAN1
-
CAN1
FLEXCAN2
-
1.6.4 Arrangement of 16-bit parallel bus
An additional feature of the CPC1001 module, which may be of interest within a number of
applications, is the possibility of organizing a high-performance 16-bit parallel bus with a
multiplexed address based on the EIM interface controller of the i.MX6 processor. The bus uses
the signals listed in Table 1.3.
