
CPC1001
C P C 1 0 0 1 U s e r M a n u a l
20
© 2 0 2 1 F a s t w e l V e r . 0 0 1
Notes
to the Table 1.1:
– The differences from the SMARC specification are highlighted in red (signal P43 (SPI0_CS0 #) -
not connected; signals P143 - P146 (CAN0 / 1) - 3.3V).
– In accordance with the SMARC specification, version 1.1, VDD_IO_SEL_D# signal (pin S158 of
the SMARC connector) is no longer designed for (compared to the SMARC 1.0 version) indication
of the voltage level VDD_IO; in CPC1001 VDD_IO=1,8 V for all the signals, except for those, for
which the voltage level of 3.3 V (auxiliary signals of SDIO, USB, PCIE, SATA and GBE interfaces),
as well as CAN0/1 signals, are set by the specification.
TOP pin
Purpose of the
SMARC connector
pins
Output of i.MX6 processor
BOTTOM
pin
Purpose of the
SMARC connector
pins
Output of i.MX6 processor
P140
SER3_TX
Not connected
S141
LCD_BKLT_PWM
SD1_DAT3
ALT3 PWM1_OUT
P141
SER3_RX
Not connected
S142
LCD_DUAL_PCK
DI0_PIN4
ALT0/1 IPU1/2_DI0_PIN4
P142
GND
-
S143
GND
-
P143
CAN0_TX
GPIO_7
ALT3 FLEXCAN1_TX
(3.3V)
S144
RSVD/EDP_HPD
Not connected
P144
CAN0_RX
GPIO_8
ALT3 FLEXCAN1_RX
(3.3V)
S145
WDT_TIME_OUT#
GPIO_9
ALT1_WDOG1_B
P145
CAN1_TX
KEY_COL4
ALT0 FLEXCAN2_TX
(3.3V)
S146
PCIE_WAKE#
KEY_COL2
ALT5 GPIO4_IO10
P146
CAN1_RX
KEY_ROW4
ALT0 FLEXCAN2_RX
(3.3V)
S147
VDD_RTC
-
P147
VDD_IN
-
S148
LID#
EIM_D20 ALT5
GPIO
P148
VDD_IN
-
S149
SLEEP#
EIM_A25 ALT5
GPIO
P149
VDD_IN
-
S150
VIN_PWR_BAD#
-
P150
VDD_IN
-
S151
CHARGING#
NANDF_CS3
ALT5 GPIO6_IO16
P151
VDD_IN
-
S152
CHARGER_PRSNT#
NANDF_CLE
ALT5 GPIO6_IO17
P152
VDD_IN
-
S153
CARRIER_STBY#
EIM_A17
ALT5 GPIO2_IO21
P153
VDD_IN
-
S154
CARRIER_PON
EIM_A16
ALT5 GPIO2_IO22
P154
VDD_IN
-
S155
FORCE_RECOV#
NANDF_CS1
ALT5 GPIO6_IO14
P155
VDD_IN
-
S156
BATLOW#
NANDF_CS2
ALT5 GPIO6_IO15
P156
VDD_IN
-
S157
TEST#
NANDF_CS0
ALT5 GPIO6_IO11
-
S158
VDD_IO_SEL_D#
GND