Description
GPS receiver
A2D–JP
Version 1.03
Side 28
2.
If SRAM checksums are invalid and EEPROM checksums are
valid, the communication parameters and initialization data
parameters will be read from EEPROM.
3.
If SRAM checksums are invalid and EEPROM checksums are
invalid, the default values in ROM will be used.
The OEM application must provide any LD/LR circuitry to extend the
range of the interface. Port Idle is nominally a CMOS logical high
(+ 3,3 V DC).
6.3.4 DC input signals
Pin 59: Preamp power input (PREAMP)
The OEM may optionally supply power to a preamplifier using the
antenna cable center conductor. The maximum voltage is +12 V DC
and the current must not exceed 100 mA.
Pins 58 and 60: Power input (PWRIN 3)
This signal is the main power input to the GPS receiver.
Regulated DC power requirements are shown in table 2.
Pin 57: Battery backup power input (VBATT)
This signal is used to provide a DC power input to the SRAM and
RTC devices only. The GPS receiver automatically switches to the
VBATT input signal when primary DC power (PWRIN) is removed
from the board.
This feature is intended to provide the GPS receiver with a "warm
start" capability by maintaining an accurate time source and using
position and satellite data stored in SRAM after prime input power
(PWRIN) has been removed from the GPS receiver.
Pins 43, 44, 46, 47 and 52: Ground (GND)
DC grounds for the board. All grounds are tied together through the
GPS receiver's printed wiring board (PWB) ground plane and should
all be grounded externally to the GPS receiver.
6.3.5 Software interface
The host serial I/O port of the GPS receiver serial data interface sup-
ports full duplex communication between the GPS receiver and the
OEM application. Data messages can be in the Conexant binary for-
mat or NMEA-01 83 format. The GPS receiver also contains an
auxiliary port dedicated to direct processing of the RTCM SC-104
messages for DGPS corrections.
Do not apply power to a passive antenna or damage to the receiver will occur.
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Содержание A2D-JP
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