© 2012 Fairchild Semiconductor Corporation
5
FEBFAN9611_S01U300A • Rev. 0.0.1
2.
Key Features
180° Out-of-Phase Synchronization
Automatic Phase Disable at Light Load
1.8A Sink, 1.0A Source, High-Current Gate Drivers
Transconductance (g
M
) Error Amplifier for Reduced Overshoot
Voltage-Mode Control with (V
IN
)
2
Feed-Forward
Closed-Loop Soft-Start with Programmable Soft-Start Time for Reduced Overshoot
Minimum Restart Timer Frequency to Avoid Audible Noise
Maximum Switching Frequency Clamp
Brownout Protection with Soft Recovery
Non-Latching OVP on FB Pin and Second-Level Latching Protection on OVP Pin
Open-Feedback Protection
Over-Current and Power-Limit Protection for Each Phase
Low Startup Current: 80µA Typical
Works with DC input or 50Hz to 400Hz AC Input
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ZCD1
ZCD2
5VB
MOT
AGND
COMP
FB
SS
OVP
CS1
CS2
PGND
DRV2
DRV1
VDD
VIN
0.2V
5V
gm
3V
REF
Q
Q
R
S
Q
Q
R
S
UVLO
5V
BIAS
5V
V
DD
V
DD
5µA
0.195V
0.195V
1.25V
I
MOT
A
B
A
B
5V
A
5V
B
PROTECTION LOGIC
(Open FB, Brownout Protection,
OVP, Latched OVP)
INPUT VOLTAGE SENSE
(Input Voltage Squarer,
Input UVLO, Brownout)
K1 V
IN
I
MOT
2
K1 V
IN
I
MOT
2
Phase
Management
CHANNEL 1
VALLEY DETECTOR
CHANNEL 2
VALLEY DETECTOR
SYNCHRONIZATION
RESTART TIMERS
FREQUENCY CLAMPS
2µA
Figure 4. Block Diagram
