© 2012 Fairchild Semiconductor Corporation
29
FEBFAN9611_S01U300A
• Rev. 0.0.1
Figure 39 and Figure 40 show the phase-adding waveforms. As observed, just before the
Channel 2 gate drive signal is enabled, the duty cycle of Channel 1 gate drive signal is
reduced by 50% to minimize the line current glitch and guarantee smooth transient. In
Figure 40, the first pulse of gate drive 2 during the phase-adding operation is skipped to
ensure 180° out-of-phase interleaving operation during transient.
CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div),
CH3: Inductor L1 Current (1A/div), CH4: Inductor L2 Current (1A/div), Time (5ms/div)
Figure 39. Phase-Adding Operation
CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div),
CH3: Inductor L1 Current (1A/div), CH4: Inductor L2 Current (1A/div), Time (5µs/div)
Figure 40. Phase-Adding Operation (Zoomed-in Timescale)
DRV1
DRV2
I
L1
I
L2
DRV1
DRV2
I
L1
I
L2
