FabiaTech FX5503, Руководство пользователя

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FabIATech Corporation
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ADVANCED CHIPSET SETUP
This section describes the configuration of the board’s chipset features.
Configure SDRAM Timing by SPD
SPD represents Serial Presence Detect. It is an 8-bit, 2048 bits EEPROM, built on the
SDRAM for 100 MHz frequencies. If the installed SDRAM supports SPD function,
select SPD. If not, you can select based on other access time of the SDRAM.
Available Options: Disabled, Enabled
Default setting: Disabled
DRAM Frequency
This specifies the SDRAM memory clock frequency.
Available Options: 100MHz, 133MHz
Default setting: 100MHz
SDRAM CAS# Latency (SCLKs)
This field specifies the latency for the Synchronous DRAM system memory signals.
Available Options: 3, 2
Default setting: 3