FabiaTech FB2631, Руководство пользователя

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PCI Latency Timer
This field specifies the latency timings (in PCI clock) PCI devices installed in the PCI
expansion bus.
Available Options: 32, 64, 96, 128, 160,192, 224, and 248
Default setting: 64
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Palette Snoop
When Enabled is selected, multiple VGA devices operating on different buses can
handle data from the CPU on each set of palette registers on every video device.
Bit 5 of the command register in the PCI device configuration space is the VGA
Palette Snoop bit. (0 is disabled).
Available Options:
Disabled: Data read and written by the CPU is only directed to the PCI VGA
devices palette registers.
Enabled: Data read and written by the CPU is directed to both the PCI VGA
devices palette registers.
Default setting: Disable
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PCI IDE BusMaster
This option is to specify that the IDE controller on the PCI local bus have bus-
mastering capability.
Available Options: Enable, Disable
Default setting: Disable
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IRQ 3 –15
When I/O resources are controlled manually, you can assign each system interrupt
as one of the following types, based on the type of device using the interrupt:
Available: Specified IRQ is available to the used by PCI/PnP devices.
Reserved: Specified IRQ is reserved for used by Legacy ISA devices.
Available Options: Available and Reserved
Default setting: Available