EWA CORELIS PXIE-1149.1/4E, Руководство пользователя, Страница: 11 / 41

Product Overview
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Hardware mechanisms enable optimal data flow between the PCIE port and the memory resources
paced by the port and/or scanning rates underway, in both directions.
A programmable, time-delay skew compensation mechanism supports the PXIE-1149.1/4E
’s high
TCK rates. It accommodates the returned, target scan stream-delays due to signal travel time down
and up the cable. It
can also adjust for a target’s internal TCK -to-TDO response delay.
Adjustable Voltage Levels
The software-programmable voltage level of the TAP interfaces and discrete I/O can be set to any
voltage between 1.25 V and 3.30 V in increments of about 0.05V. Each of the four TAPs has its
own programmable voltage settings.
Discrete Input/Output Signals
The PXIE-1149.1/4E operates three discrete input/output signals under software control. These
attach to the target TAP connector. They are driven or sensed as directed by software, in
coordination with the scanning operation. Each signal can be configured independently as TTL
output, open-collector (open-drain) output, or as input at the programmable voltage level. As open-
collector drivers, they can readily tie to similar target signals without the need to alter its circuitry, yet
still gain control of related functions, such as a Flash write signal.
As outputs, these discrete signals are useful for providing control functions on the user target system
such as general reset, power control, device write pulse, disable/enable and/or similar signals for
non-boundary-scan target stimulus.
Conversely, as inputs, they enable host sensing of the target to pace scanning activity or related
conditions (such as a Flash ready signal).
PXIE Interface
The PXIE-1149.1/4E is a PXI peripheral module that fits in a 3U slot utilizing 1 lane of PCIe. This
PXI interface supplies the power to operate the PXIE-1149.1/4E. The PXIE-1149.1/4E is not hot
pluggable. Power should be off while install and removing the PXIE-1149.1/4E controller.
Programmable Clocks
The PXIE-1149.1/4E ’s programmable TCK output to the IEEE Standard 1149.1 compatible target
system can be configured over a wide range of frequencies, using on-board clock-generation
circuitry. A programmable Phase Locked Loop (PLL) enables a wide range as well as fine- selection
resolution. See Table 1-1 for the set of programmable values.
TCK range (MHz) Rate Resolution (MHz)
15 to 75 1
1 to 15 0.5
0.05 to 1 0.05
Table 1-1. Programmable TCK Frequencies