
54
CS
CLK
MOSI
MISO
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
B7
B7
B6
B6
B5
B5
B4
B4
B3
B3
B2
B2
B1
B1
B0
B0
T1
Figure 5.1
As Figure 5.1 shows the clock idle state is high. On a falling edge of the clock the module switches the state of the
data line (MISO) and on a rising edge of the clock the module samples the data line (MOSI). During transmission, the
most significant bit is transmitted first. One frame is eight bits long (one byte). The CS signal is active low thus the
master must drive the CS signal low before clocking the clock signal. The maximum clock frequency for the system is
500 kHz. An additional restriction is also placed on the minimum allowed time between the CS line going low and
the first clock falling edge and the minimum allowed time for CS being high between transmission (please see
chapter 2.7). This is the result of low power consumption as the system must jump from sleep state to run state at
various points during communication.
5.2.2
Exchanging data (reading or reading and writing)
The SPI bus is a type of synchronous bus where both sides (master and slave) synchronised by the master clock send
data at the same time in both directions. Each transmission is initiated when the master drives the CS line low and
ends when the CS line is driven high. All bytes transmitted in each direction between falling and rising edge of the CS
line are considered as one packet and bytes within those packets are ordered. The First byte is transmitted always
after the falling edge of the CS signal. A typical packet exchange is shown in Table 5.1.
Table 5.1
1
2
3
4
3 + n
Value
0x00 - 0xFF
0x00 - 0xFF
0x00, 0x01
0x00 - 0xFF
0x00 - 0xFF
Type
Address LSByte Address MSByte
0x00 - Read,
0x01 - Read and
Write
Data Byte 1
……..
Data Byte n
Value
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
0x00 - 0xFF
Type
Trash data
Trash data
Trash data
Data Byte 1
……..
Data Byte n
Byte number
MOSI
MISO
Содержание RFID A1
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