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5
Communication Interface
5.1
nBUSY line
The RFID A1 Module provides two communication buses: SPI Slave and I2C Slave. Each of these buses has an equal
level of access to the module internal registers. These buses operate independently but the user cannot use both at
the same time. The module has no safety system and doing so can make the system work in unpredictable ways.
The RFID A1 Module provides nBUSY signal line which shares the functionality between both communication buses.
This signal line is configured as an output. The nBUSY signal is driven low by the module when anything is written to
the memory. At the same time when nBUSY line is driven low the result register is set to 0xFF value. This inform the
user that module is busy and is parsing data or executing command and nothing else should be written to the
module now. The user must wait for nBUSY line going high or Result Register value changing from 0xFF to perform
any operation on the module or to read any data from the module which is a result of current processing.
5.2
SPI Bus
The RFID A1 Module provides a SPI slave bus. This is one of two buses provided by the module. It is the fastest
communication option in the module. The high clock frequency together with simultaneous communication in both
directions gives the fastest data exchange rate, but requires the most number of IO lines.
5.2.1
Bus signals and timings requirements
There are four signals necessary for communication via SPI bus. These are CLK, MOSI, MISO and CS. CLK (Clock), CS
(Chip Select) and MOSI (Master Out Slave In) signals are controlled by the master on every transmission and these
pins on the RFID A1 module are configured as inputs without any pull-up or pull-down resistors. MISO (Master In
Slave Out) signal is driven by the module to Vcc and to ground when there is ongoing transmission. During
communication via the SPI bus the user must pay attention to the nBUSY signal or must be sure that the Result
Register has other value than 0xFF when writing to the module.
The SPI frame timing together with clock polarisation and phase is shown in Figure 5.1.
Содержание RFID A1
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