Marconi OMS 1200
Technical Product Description
221 02-ZAP 701 25/1 Rev C 2006-08-04
© Ericsson AB 2006
03PHB00004AAV-CUA
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Core Card Failure Monitoring by CCU Function and Using Hardware
Control Lines
A hardware logic circuit scheme, along with hardwired monitor and control lines allows
the CCU controller function to detect catastrophic failure/removal of a core card, and
initiate fast master/slave switching between core cards (and their dependant core
tributaries in OMS1240 products).
The nature and behaviour of the scheme is covered in the following subsections.
Core Card Switch to Line Span Protection Traffic Interface Clock Failure
Monitoring – (STM-1/4 Core Cards)
A further switching criterion applies, related to core cards monitoring each other for
failure.
Switch–to-line span protection pSTM-1 traffic interfaces are crossover tracked
between core cards and each card receives switch–to-line and line–to-switch
crossover (pT0) signal clocks from its partner.
After power-up initialisation and CCU configuration of a core card, partner core clock
failures are detected and reported by each core card to its traffic uController, during
routine ASIC polling cycles. The uController interprets these as a partner core card
failure/removal state and this is a trigger for a core card (and its dependant core
tributary in OMS 1240 products) to autonomously take over master status if it is
currently in slave status. It effects a master/slave switchover sequence, just as it
would if it received a master status interrupt from the CCU controller via the hardware
control lines mentioned above.
If a core card is currently in master status, clock failure detection of its slave partner
does not invoke any autonomous master/slave switching actions; this to the extent
that no spurious switch actions occur upon insertion/extraction/failure of current slave
cards.
•
Detecting clock failures from a core card implies a catastrophic
ASIC/hardware failure. In this case peripheral traffic interface cards and core
traffic modules are assumed to also detect core switch failure (via SDMs)
and autonomously switch core traffic signals in parallel.
•
The design ensures that clock failure monitoring is negated during insertion,
power-up and initialisation of a core card.
•
A core card does not initiate the master/slave switchover sequence if the
CCU controller has previously invoked a master/slave switch due to an
operator Forced Switch command. A core card Controller will receive
master/slave switching messages over the CCU control busses, either in
reaction to autonomous switching actions, or in response to operator Forced
Switch commands.
•
If a core card is currently responding to master/slave switching instructions
from the CCU controller, concurrent detection of clock failures from its
partner takes priority and the core card takes over master status.
•
In OMS 1240 systems, master status takeover invokes a full core card and
core tributary function takeover, though acknowledging the fact that SETG
function master/slave switching is prevented.
