Epson S1C62 Family, Справочное руководство

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Format
ICE CONTROL SOFTWARE ICS62XX
VIII-54
EPSON
S1C62 FAMILY
DEVELOPMENT TOOL REFERENCE MANUAL
Function
BR, BRR
SET/RESET BREAK REGISTER CONDITION
#BR
(With guidance)
#BRR
A break condition is set in the evaluation board CPU registers A, B, FLAG, X (Xp, Xh, Xl,) or
Y (Yp, Yh, Yl).
(1) BR: A break condition is set in the target registers A, B, FLAG, X (Xp, Xh, Xl,) or Y
(Yp, Yh, Yl). The break condition in each register can be masked (a masked
register can generate a break in another register, whatever the specified value).
Break is induced when the values of each register correspond to the set values in
the internal CPU registers.
(2) BRR: Cancels a break condition set by BR command.
(3) A break set by the BR command is operative at one point. BA and BD settings can be
mixed.
(4) A BR condition can be canceled by executing the BM command.
Examples
#BR
A -:C
... A hyphen (-) is displayed when a BR condition is not set
B -:*
Break condition is sequentially set
FI -:1
FD -:*
... Enter an asterisk (*) mark to indicate masking
FZ -:0 This induces a break unrelated to the FD value
FC -:*
X ---:040
Y ---:^
... If a parameter is mis-set, entering the ^ key will return
X ---:041 the operation to the previous setting (one less than the
Y ---:030 current setting)
A break condition set as described above, where A=C, FI=1, FZ=0, X=41, and Y=30.
#BR
A C:
...
Reads a previously set break condition
B *: When no setting modification is made, hitting the key
FI 1:* continues the operation to the next setting
FD *:
FZ 0:*
FC *:
X 041:042
Y 030:*
Two break conditions where A=C and X=42 are described above.