Epson S1C62 Family, Справочное руководство

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ICE CONTROL SOFTWARE ICS62XX
S1C62 FAMILY
EPSON
VIII-13
DEVELOPMENT TOOL REFERENCE MANUAL
(3) Execution time mode and step number mode can be set during run time (using the #TIM command).
Millisecond is abbreviated to "mS". In step number mode, decimal values describe the run time, as in :
"
*RUN TIME=501 STEPS
".
When the execution time or step counters overflow, the message "
*RUN TIME=TIMEOVER
" is
displayed. For more details, see Section 2.3.10, "Measurement during command execution".
2.3.5
Break assigning commands
The ICE has a variety of break setting functions.
(1) Set break by PC:
Set by the BA command. The instruction is executed when the evaluation board CPU PC and the set
values agree, thus inducing a break. When the PSET command is entered at the set address, the PSET
and subsequent instruction are executed, then processing is halted. (When multiple PSET commands
are specified, the instructions are executed until a command other than PSET is encountered.)
Breaks can be set for multiple PC's (to the maximum capacity of program memory).
(2) Set break by RAM data:
Set by the BD command. A break is induced by the RAM data address, data, or R/W AND condition.
Also, masks can be set for address, data and R/W respectively.
When a break is induced by writing F data at address 10, the settings are: address=10, data=F, R/W=W.
Any data can be used with the following settings: address=10, data=mask, R/W=W. A break will occur
after execution of the memory access instruction which equals the set conditions. The break point can be
set to one point through these settings.
(3) Set break by register value:
Set by BR command. When the register values of the evaluation board CPU coincide with the set break
values, a break is initiated following execution of the instruction.
A break is induced by and AND condition set in the A, B, FI, FD, FZ, FC, X, or Y registers. Also, a mask
can be set in any of the registers. When a break is induced with register A=5, X=70, and Y=0A, the other
registers may be masked.
Example:
LD A,5
LD X,70
LD Y,0A
. . . A break is induced when the above instruction is executed.
These settings will allow the operation to run in real time. The break point can be set at only one point.
Items (1), (2) and (3) above can be set independently.
When BA, BD and BR are set concurrently, a break will occur when any of the conditions coincide.
(4) Set compound break:
Set by BM command. A compound break occurs when breaks (1), (2) and (3) include AND statements.
Breaks can have the following elements masked: (coincide with PC), (coincide with RAM data address,
data, R/W), (register value). The break point can be set at only one point. At the current setting, setting
(1) through (3) are automatically canceled. If settings (1) through (3) follow the current setting, the BM
condition is canceled.
Note Since the RAM data condition is a break element, the break will not be initiated without instructions
which access the RAM data.