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RA8900 SA / CE

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ETM44E-01

VLF

Data Description

Write

0

The VLF bit is cleared to zero to prepare for the next status detection.

1

This bit is invalid after a "1" has been written to it.

Read

0

Data loss is not detected.

1

Data loss is detected. All registers must be initialized.
( This setting is retained until a "zero" is written to this bit. )

5) VDET ( Voltage Detection Flag ) bit

This flag bit indicates the status of temperature compensation. Its value changes from "0" to "1" when stop the
temperature compensation, such as due to a supply voltage drop. Once this flag bit's value is "1", its value is
retained until a "0" is written to it.
When after powering up from 0 V this bit's value is "1".

VDET

Data Description

Write

0

The VDET bit is cleared to zero to prepare for the next low voltage detection.

1

The write access of "1" to this bit is invalid.

Read

0

Temperature compensation is normal.

1

Temperature compensation is stop detected.

8.2.7. Control register

Address

Function

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0F, 1F

Control Register

CSEL1

CSEL0

UIE

TIE

AIE





RESET

(Default)

(0)

(1)

(



)

(



)

(



)

(0)

(0)

(



)



1)



The default value is the value that is read (or is set internally) after powering up from 0 V.



2)



"o" indicates write-protected bits. A zero is always read from these bits.



3)



"



" indicates no default value has been defined.



This register is used to control interrupt event output from the /INT pin and the stop/start status of clock and

calendar operations.

1) CSEL0,1 ( Compensation interval Select 0, 1 ) bits

The combination of these two bits is used to set the temperature compensation interval.

CSEL0,1

CSEL1

(bit 7)

CSEL0

(bit 6)

Compensation interval

Write/Read

0 0 0.5

s

0 1 2.0

s



Default

1 0 10

s

1 1 30

s

2) UIE ( Update Interrupt Enable ) bit

When a time update interrupt event is generated (when the UF bit value changes from "0" to "1"), this bit's value
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status
remains Hi-Z).
When a "1"



is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an

interrupt event is generated.
When a "0"



is written to this bit, no interrupt signal is generated when an interrupt event occurs.

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Содержание RA8900SA/CE

Страница 1: ...ETM44E 01 Preliminary Application Manual Real Time Clock Module RA8900SA CE ...

Страница 2: ...nd any technical information furnished if any for the development and or manufacture of weapon of mass destruction or for other military purposes You are also requested that you would not make the products available to any third party who may use the products for such prohibited purposes These products are intended for general use in electronic equipment When using them in specific applications th...

Страница 3: ...ram 18 8 4 2 Related registers for time update interrupt functions 19 8 5 Alarm Interrupt Function 20 8 4 1 Diagram of alarm interrupt function 20 8 5 2 Related registers 21 8 5 2 Examples of alarm settings 22 8 6 About the interrupt function for operation INT L interrupt output 23 8 7 Temperature compensation function 23 8 7 1 Temperature compensation function 23 8 7 2 Related registers for tempe...

Страница 4: ... changed until it releases 1 Overview This module is an I 2 C bus interface compliant real time clock which includes a 32 768 kHz DTCXO In addition to providing a calendar year month date day hour minute second function and a clock counter function this module provides an abundance of other functions including an alarm function fixed cycle timer function time update interrupt function and 32 768 k...

Страница 5: ...the FOUT pin Hi Z high impedance FOE Input This is an input pin used to control the output mode of the FOUT pin When this pin s level is high the FOUT pin is in output mode When it is low output via the FOUT pin is stopped INT Output This pins is used to output alarm signals timer signals time update signals and other signals This pin is an open drain pin VBAT This is a power supply pin for backup...

Страница 6: ... 5 V Temp compensation voltage VTEM Temperature compensation voltage 2 0 3 0 5 5 V Clock supply voltage VCLK 1 6 3 0 5 5 V Operating temperature TOPR No condensation 40 25 85 C 6 Frequency Characteristics GND 0 V Item Symbol Condition Rating Unit Frequency stability f f U A Ta 0 to 50 C VDD 3 0 V Ta 40 to 85 C VDD 3 0 V 1 9 1 3 4 2 10 ６ U B Ta 0 to 50 C VDD 3 0 V Ta 40 to 85 C VDD 3 0 V 3 8 3 5 0 ...

Страница 7: ...D 5 V 0 70 1 45 A Current consumption 8 IDD8 VDD 3 V 0 68 1 35 Current consumption 9 IDD9 fSCL 0 Hz INT VDD FOE GND VDD VBAT FOUT output OFF High Z Compensation ON peak VDD 5 V 55 100 A Current consumption 10 IDD10 VDD 3 V 50 95 High level input voltage VIH CE DI CLK FOE pins 0 8 VDD 5 5 V Low level input voltage VIL CE DI CLK FOE pins GND 0 3 0 2 VDD V High level output voltage VOH1 FOUT pin VDD ...

Страница 8: ...SCL H tHIGH 0 6 s Rise time for SCL and SDA tr 0 3 s Fall time for SCL and SDA tf 0 3 s Allowable spike time on bus tSP 50 ns FOUT duty tW t 50 of VDD level 40 50 60 Timing chart tHD DAT tSU DAT tHD STA tLOW tHIGH 1 fSCL tr tf tSU STA SDA SCL START CONDITION S BIT 7 MSB A7 BIT 6 A6 ACK A Protocol tBUF tSU STO STOP CONDITION P START CONDITION S P A tHD STA tSU STA S BIT 0 LSB R W S tSP Caution When...

Страница 9: ...P 0D Extension Register TEST WADA USEL TE FSEL1 FSEL0 TSEL1 TSEL0 P P 0E Flag Register UF TF AF VLF VDET P P 0F Control Register CSEL1 CSEL0 UIE TIE AIE RESET P P P Possible I Impossible Note When after the initial power up from 0 V or when the result of read out the VLF bit is 1 initialize all registers before using the module Be sure to avoid entering incorrect date and time data as clock operat...

Страница 10: ...15 MONTH 10 8 4 2 1 P P 16 YEAR 80 40 20 10 8 4 2 1 P P 17 TEMP 128 64 32 16 8 4 2 1 P P 18 Backup Function VDET OFF SWOFF BKSMP1 BKSMP0 P P 19 Not use P P 1A 1B Not use 128 P P Timer Counter 0 64 32 16 8 4 2 1 1C Timer Counter 1 2048 1024 512 256 P P 1D Extension Register TEST WADA USEL TE FSEL1 FSEL0 TSEL1 TSEL0 P P 1E Flag Register UF TF AF VLF VDET P P 1F Control Register CSEL1 CSEL0 UIE TIE A...

Страница 11: ...data may interfere with normal operation of the clock counter 1 Second counter Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 10 SEC 40 20 10 8 4 2 1 This second counter counts from 00 to 01 02 and up to 59 seconds after which it starts again from 00 seconds 2 Minute counter Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 11 MIN 40 20 10 8 4 2 1 This minute...

Страница 12: ...om these bits The auto calendar function updates all dates months and years from January 1 2001 to December 31 2099 The data format is BCD format For example a date register value of 0011 0001 indicates the 31st Note with caution that writing non existent date data may interfere with normal operation of the calendar counter 2 Date counter Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 ...

Страница 13: ...efault value is the value that is read or is set internally after powering up from 0 V 2 o indicates write protected bits A zero is always read from these bits 3 indicates a default value is undefined This register is used to specify the target for the alarm function or time update interrupt function and to select or set operations such as fixed cycle timer operations 1 TEST bit This is the manufa...

Страница 14: ...to detect the occurrence of various interrupt events and reliability problems in internal data 1 UF Update Flag bit If set to 0 beforehand this flag bit s value changes from 0 to 1 when a time update interrupt event has occurred Once this flag bit s value is 1 its value is retained until a 0 is written to it For details see 8 4 Time Update Interrupt Function 2 TF Timer Flag bit If set to 0 beforeh...

Страница 15: ...bit 3 bit 2 bit 1 bit 0 0F 1F Control Register CSEL1 CSEL0 UIE TIE AIE RESET Default 0 1 0 0 1 The default value is the value that is read or is set internally after powering up from 0 V 2 o indicates write protected bits A zero is always read from these bits 3 indicates no default value has been defined This register is used to control interrupt event output from the INT pin and the stop start st...

Страница 16: ... Alarm Interrupt Enable bit When an alarm timer interrupt event occurs when the AF bit value changes from 0 to 1 this bit s value specifies if an interrupt signal is generated INT status changes from Hi Z to low or is not generated INT status remains Hi Z When a 1 is written to this bit an interrupt signal is generated INT status changes from Hi Z to low when an interrupt event is generated When a...

Страница 17: ...p power supply function register Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 18 Backup Function VDET OFF SWOFF BKSMP1 BKSMP0 This register is a setting register the voltage detection of VDD and built in MOS switch of anti countercurrent control 1 VDETOFF bit Voltage Detector OFF This bit controls the voltage detection circuit of the main power supply VDD For details see 8 Func...

Страница 18: ...ed cycle timer stops 1 1 2 001 h 000 h 3 4 5 1 6 7 7 7 8 9 1 When a 1 is written to the TE bit the fixed cycle timer countdown starts from the preset value 2 A fixed cycle timer interrupt event starts a countdown based on the countdown period source clock When the count value changes from 001h to 000h an interrupt event occurs After the interrupt event that occurs when the count value changes from...

Страница 19: ...ve according to the source clock setting 2 When the source clock has been set to second update or minute update the timing of both countdown and interrupts is coordinated with the clock update timing 2 Fixed cycle Timer Control register Reg B to C This register is used to set the default preset value for the counter Any count value from 1 001 h to 4095 FFFh can be set The counter counts down based...

Страница 20: ... 3 3 Fixed cycle timer interrupt interval example Timer Counter setting Source clock 4096 Hz TSEL1 0 0 0 64 Hz TSEL1 0 0 1 Second update TSEL1 0 1 0 Minute update TSEL1 0 1 1 0 1 244 14 s 15 625 ms 1 s 1 min 2 488 28 s 31 25 ms 2 s 2 min 41 10 010 ms 640 63 ms 41 s 41 min 205 50 049 ms 3 203 s 205 s 205 min 410 100 10 ms 6 406 s 410 s 410 min 2048 500 00 ms 32 000 s 2048 s 2048 min 4095 0 9998 s 6...

Страница 21: ...eared to zero Operation in RTC i i Write operation 1 2 3 4 1 5 6 7 1 A time update interrupt event occurs when the internal clock s value matches either the second update time or the minute update time The USEL bit s specification determines whether it is the second update time or the minute update time that must be matched 2 When a time update interrupt event occurs the UF bit value becomes 1 3 W...

Страница 22: ... from 0 to 1 when a time update interrupt event occurs When this flag bit 1 its value is retained until a 0 is written to it UF Data Description Write 0 The UF bit is cleared to zero to prepare for the next status detection Clearing this bit to zero does not enable the INT low output status to be cleared to Hi Z 1 This bit is invalid after a 1 has been written to it Read 0 Time update interrupt ev...

Страница 23: ...ime is used as the setting the alarm will not occur until the counter counts up to the current date time i e an alarm will occur next time not immediately 2 When a time update interrupt event occurs the AF bit values becomes 1 3 When the AF bit 1 its value is retained until it is cleared to zero 4 If AIE 1 when an alarm interrupt occurs the INT pin output goes low When an alarm interrupt event occ...

Страница 24: ...et The WADA bit is used to specify either WEEK or DAY as the target for alarm interrupt events WADA Data Description Write Read 0 Sets WEEK as target of alarm function DAY setting is ignored 1 Sets DAY as target of alarm function WEEK setting is ignored 2 Alarm registers Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 08 18 MIN Alarm AE 40 20 10 8 4 2 1 09 19 HOUR Alarm AE 20 10 8...

Страница 25: ...rom low to Hi Z Even when the AIE bit value is 0 another interrupt event may change the INT status to low or may hold INT L 1 When an alarm interrupt event occurs an interrupt signal is generated INT status changes from Hi Z to low When an alarm interrupt event occurs low level output from the INT pin occurs only when the AIE bit value is 1 This value is retained not automatically cleared until th...

Страница 26: ...f our company is set by built in memory Oscillation frequency for a temperature change is compensated This function cannot stop with the high operation voltage than temperature compensation operation voltage VTEM 8 7 2 Related registers for temperature compensation function Address h Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0F 1F Control Register CSEL1 CSEL0 UIE TIE AIE RESET 1 CSE...

Страница 27: ...en an drive power source changes to VDD OFF VBAT it shifts to a backup operation from a normal operation it becomes possible to prevent a reverse current VBAT VDD of an electric current Connection example VDD VBAT VDD C VDD VBAT secondary battery VDD EDLC or R C C VDD VBAT primary battery VDD R C C Connection example when not using the battery backup switchover function If you do not want to use t...

Страница 28: ...ed in the off timing of the switch Off time of the switch can be selected in the register Drop of the main power supply is detected an internal power supply voltage of the RTC will be backed up state transitions 8 8 3 Function that can be used in the backup state When operating in the backup please VDD VSS 0V Function Available Not available Remarks Interface Not available Interface circuit can no...

Страница 29: ...voltage detection to the next period VBAT VDD between PMOS switch remains on Because VDD voltage detection operate every second between VBAT VDD become a short circuit condition about one second 8 8 5 Related registers of the backup power supply switching function Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 18 Backup Function VDET OFF SWOFF BKSMP1 BKSMP0 VDETOFF SWOFF BKSMP1 B...

Страница 30: ...its slave address matches the slave address in the received data In either case the data is transferred via the SCL line at a rate of one bit per clock pulse 8 9 2 System configuration All ports connected to the I2 C bus must be either open drain or open collector ports in order to enable AND connections to multiple devices SCL and SDA are both connected to the VDD line via a pull up resistance Co...

Страница 31: ... stopped at any time while in progress However this is only when this RTC module is in receiver mode data reception mode SDA released 3 When communicating with this RTC module the series of operations from transmitting the START condition to transmitting the STOP condition should occur within 0 95 seconds A RESTART condition may be sent between a START condition and STOP condition but even in such...

Страница 32: ...pulse corresponding to the 8th bit of data on the SCL line the transmitter releases the SDA line and the receiver sets the SDA line to low acknowledge level SCL from Master SDA from transmitter sending side ACK signal 1 2 8 9 SDA from receiver receiving side Release SDA Low active After transmitting the ACK signal if the Master remains the receiver for transfer of the next byte the SDA is released...

Страница 33: ...900 6 CPU transfers RESTART condition Sr in which case CPU does not transfer a STOP condition P 7 CPU transfers RA8900 s slave address with the R W bit set to read mode 8 Check for ACK signal from RA8900 from this point on the CPU is the receiver and the RA8900 is the transmitter 9 Data from address specified at 4 above is output by the RA8900 10 CPU transfers ACK signal to RA8900 11 Repeat 9 and ...

Страница 34: ...al setting by the software command Item Symbol Condition Min Typ Max Unit Detection voltage 1 VDET 1 9 1 95 2 0 V Detection voltage 2 VLOW 1 16 1 60 V Detection voltage 3 VDET3 2 3 2 4 2 5 V Power supply rise time1 tR1 VDD VSS to 2 5V 1 10 ms V Access wait time Initial power on tCL After VDD 2 5V 30 ms Chip disable wait time tCD After stop condition 0 s V Power supply fall time tF VDD 2 5V to VSS ...

Страница 35: ...o read VLF bit first 2 When a reading result of VLF bit is 1 please initialize all registers Please perform initial setting after progress in the oscillation start time when inside oscillation is stable 3 Access is prohibited till 30ms passes after surpassing bottom value of clock supply voltage VDD 1 6V VDD VCLK Min V Internal OCS tSTA s An interface operation is possible A clock operation is pos...

Страница 36: ...the present time concerned please refer to item of Clock and calendar writing Setting the Alarm function Set the Alarm interrupt function When the alarm interrupt function is not being used the Alarm registers can be used as a RAM register In such cases be sure to write 0 to the AIE bit Setting the Timer function Set the fixed cycle Timer function When the fixed cycle timer function is not being u...

Страница 37: ...n this case after an internal oscillation begins it is necessary to clear VLF 0 When an internal oscillation starts 0 writing of VLF is approved Start up complete power on Wait Wait time of 30ms is necessary at least Whether it is a return from the state of the backup is confirmed VLF 1 YES YES NO VLF 0 clear Wait VLF 0 Software reset Initialize NO Please set waiting time depending on load of a sy...

Страница 38: ...ess within 0 95 seconds RESET 1 Set RESET bit to 1 to prevent timer update in time setting 4 The reading of a clock and calendar Next process Reading of the clock Read clock Please complete access within 0 95 seconds At the time of a communication start the Clock Calendar data are fixed hold the carry operation and it is automatically revised at the time of the communication end The access to a cl...

Страница 39: ...RA8900 SCL SDA GND VDD I C BUS 2 I 2 C Bus VDD Note SDA SCL SLAVE ADRS 0110 010 VBAT Note It uses the secondary battery or a lithium battery For detailed value on the resistance please consult a battery maker 8 14 When used as a clock source 32 kHz TCXO RA8900 VDD T1 GND 0 1 F FOUT INT SCL SDA FOE VDD 32 768kHz O E VBAT VDD ...

Страница 40: ...mm 10 1 0 2 5 0 7 4 0 2 14 8 7 1 1 27 1 2 0 05 Min 3 2 0 1 0 35 The cylinder of the crystal oscillator can be seen in this area front but it has no affect on the performance of the device 9 1 2 Marking layout RA8900SA SOP 14pin Logo Type Production lot A8900 A E A123B Frequency Stability UA A UB Blank UC C Contents displayed indicate the general markings and display but are not the standards for t...

Страница 41: ...g pattern 0 7 0 4 Unit mm 3 2 0 2 2 5 0 2 1 0Max 0 7 0 3 0 62 0 9 1 1 0 35 0 3 9 2 2 Marking layout RA8900CE 1 Pin Mark Logo Production lot A8900 A A123B Type UA A UB Blank UC C Frequency Stability Contents displayed indicate the general markings and display but are not the standards for the fonts sizes and positioning ...

Страница 42: ... If the temperature within the package exceeds 260 C the characteristics of the crystal oscillator will be degraded and it may be damaged The reflow conditions within our reflow profile is recommended Therefore always check the mounting temperature and time before mounting this device Also check again if the mounting conditions are later changed See Fig 2 profile for our evaluation of Soldering he...

Страница 43: ...nghai Branch High Tech Building 900 Yishan Road Shanghai 200233 China Phone 86 21 5423 5577 Fax 86 21 5423 4677 Shenzhen Branch 12 F Dawning Mansion 12 Keji South Road Hi Tech Park Shenzhen China Phone 86 755 2699 3828 Fax 86 755 2699 3838 EPSON HONG KONG LTD Unit 715 723 7 F Trade Square 681 Cheung Sha Wan Road Kowloon Hong Kong Phone 86 755 2699 3828 Shenzhen Branch Fax 86 755 2699 3838 Shenzhen...

Страница 44: ...62 01 00 Fax 32 0 2 462 01 25 belgium texim europe com Denmark Sdr Jagtvej 12 DK 2970 Hørsholm Tel 45 88 20 26 30 Fax 45 88 20 26 39 nordic texim europe com The Netherlands Elektrostraat 17 NL 7483 PG Haaksbergen Tel 31 0 53 573 33 33 Fax 31 0 53 573 33 30 nl texim europe com Germany Martin Kollar Strasse 9 D 81829 München Tel 49 0 89 436 086 0 Fax 49 0 89 436 086 19 germany texim europe com Germa...

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