Epson LX-HOO, Техническое руководство

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REV.-B
Pin
Number
45
46
47
54
55
62
63
64
Port
WR
ALE
V
D D
Vcc
Table 2-3. CPU Port Assignment (cent’d)
o
0
0
I
I
Signal Line
Name
WR
ALE
A 8
A 15
(AO)
(A7)
Description
Memory write timing strobe signal. Connected to the WR
strobe terminal of the gate array and the write enable terminal
of the RAM.
Address latch enable signal. Controls address latching per-
formed inside the gate array (enables latching when the signal
is HIGH).
8-bit ports with output latch. Used as the upper address
bus according to the MODE 0/1 terminal selection. For 64K
external memory assignment), Al 3 through Al 5 are input to
the address decoder in the gate array.
Multiplexed bus. Used as the lower address and
data bus.
Power supply for the internal RAM (+5
Power supply for the CPU When this voltage is not
stable, such as at either a leading or trailing edge (when the
printer power is turned on or off), the reset circuit prevents the
CPU from running.
NOTES: 1. All barred signal are LOW active.
2. “1/0” denotes either input or output when viewing the signal from the CPU.
2-13