MAINBOARD BIOS SETUP
BIOS, Driver & Utility Guide
15
Chipset Features Setup
This setup menu contains advanced configuration options relating to the
mainboard chipset. These options are rarely changed by the user.
SDRAM RAS-to-CAS Delay
: 3
Auto Detect DIMM/PCI Clk
: Enabled
SDRAM RAS Precharge Time
: 3
Spread Spectrum
: Disabled
SDRAM CAS latency Time
: 3
CPU Host Clock
: Default
SDRAM Precharge Control
: Disabled
Current CPU Temperature
: 47
°
C/116
°
F
DRAM Data Integrity Mode
: Non-ECC
Current CPU FAN Speed
: 5400 RPM
System BIOS Cacheable
: Enabled
Current System FAN speed
: 0 RPM
Video BIOS Cacheable
: Enabled
Vcore
: 2.81V
+ 3.3V
: 3.36V
Video RAM Cacheable
: Enabled
+ 5V
: 5.14V
+ 12V
: 12.16V
8 Bit I/O Recovery Time
: 1
- 12V
: -12.35V
- 5V
: - 5.04V
16 Bit I/O Recovery Time
: 1
Memory Hole At 15M-16M
: Disabled
CPU Warning Temperature
: Disabled
Passive Release
: Enabled
CPU FAN Warning Speed
: Disabled
Delayed Transaction
: Enabled
System 5V Alarm
: Disabled
AGP Aperture Size (MB)
: 64
ESC : Quit
↑
↓
→
←
: Select Item
F1 : Help PU/PD/+/- : Modify
F5 : Old Values (Shift) F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
SDRAM RAS-to-CAS Delay
–
This option allows you to determine the number of
clocks allocated between the assertion of RAS to CAS. Do not change the value in
this field unless you change to different DRAM or CPU with different
specifications.
SDRAM RAS Precharge Time
–
Defines the length of time that
R
ow
A
ddress
S
trobe is allowed to precharge. If insufficient time is allowed, refresh may be
incomplete and data will be lost.
SDRAM CAS Latency Time
- This item allows you to select the CAS# latency for
all SDRAM cycles. Options are 3 or 2 Clocks.
SDRAM Precharge Control
- Determines the SDRAM precharge control action
taken when a page miss occurs.
Enabling
this option allows precharge only the
bank targeted by the page miss cycle.
DRAM Data Integrity Mode –
When set at
Non-ECC
, there will be no memory
errors shown on the monitor for Memory parity SERR# (NMI). When parity
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