6.1.4 General Purpose Timer (GPT)
Using pin multiplexing 's features we may have the following GPT connections. In the tables below are shown the signals on the
Connector's module.
GPT IN interfaces
Pin number
Pin Name on i.MX
Signal reference
Voltage reference
33 / 112
GPIO1_IO00 / UART2_TX_DATA
GPT 1 - CAPIN1
+3,3V
113 / 132
UART2_RX_DATA / ENET1_RX_ER
GPT 1 - CAPIN2
+3,3V
185
SD1_DATA2
GPT 2 - CAPIN1
+3,3V
186
SD1_DATA3
GPT 2 - CAPIN2
+3,3V
Table 33
GPT OUT interfaces
Pin number
Pin Name on i.MX
Signal reference
Voltage reference
28 / 116
GPIO1_IO01 / UART1_TX_DATA
GPT1_CMPOUT1
+3,3V
27 / 120
GPIO1_IO02 / UART2_CTS_B
GPT1_CMPOUT2
+3,3V
27 / 121
UART2_RTS_B
GPT1_CMPOUT3
+3,3V
19
SD1_CMD
GPT2_CMPOUT1
+3,3V
189
SD1_CLK
GPT2_CMPOUT2
+3,3V
188
SD1_DATA0
GPT2_CMPOUT3
+3,3V
Table 34
GPT CLK interfaces
Pin number
Pin Name on i.MX
Signal reference
Voltage reference
117
UART1_RX_DATA
GPT1_CLKIN
+3,3V
187
SD1_DATA1
GPT2_CLKIN
+3,3V
Table 35
D N :
4 4