6.1.8 uSDHC Interfaces
uSDHC
Interface (SD1)
Pin Number
Pin Name on i.MX
Signal reference
Voltage reference
26 / 68 / 183
GPIO1_IO03 / CSI_DATA05 / UART1_RTS_B
uSDHC1 CD Signal
+3,3V
188
SD1_DAT0
uSDHC1 DAT 0 signal
+3,3V
187
SD1_DAT1
uSDHC1 DAT 1 signal
+3,3V
185
SD1_DAT2
uSDHC1 DAT 2 signal
+3,3V
186
SD1_DAT3
uSDHC1 DAT 3 signal
+3,3V
189
SD1_CLK
uSDHC1 CLK signal
+3,3V
190
SD1_CMD
uSDHC1 CMD signal
+3,3V
Table 49
uSDHC Interface (SD2)
1)
Pin Number
Pin Name on i.MX
Signal reference
Voltage reference
37
/ 183
CSI_MCLK / UART1_RTS_B
uSDHC2 CD Signal
+3,3V
108 / 168
LCD_DATA20 / CSI_DATA00
uSDHC2 DAT 0 signal
+3,3V
109 / 171
LCD_DATA21 / CSI_DATA01
uSDHC2 DAT 1 signal
+3,3V
65 / 170
LCD_DATA22 / CSI_DATA02
uSDHC2 DAT 2 signal
+3,3V
106 / 166
LCD_DATA23 / CSI_DATA03
uSDHC2 DAT 3 signal
+3,3V
16 / 169
LCD_DATA19 / CSI_VSYNC
uSDHC2 CLK signal
+3,3V
15 / 167
LCD_DATA18 / CSI_HSYNC
uSDHC2 CMD signal
+3,3V
Table 50
1)
For the module equipped with eMMC the SD2 interface is not available
. In this configuration, the pins in the table above, are
always available for all the other alternative functions selectable by the processor's IOMUX,
except the SD2 peripheral
that is used for
the manage of the eMMC interface.
D N :
4 9