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EDM 01-18 DAG 4.5G2/G4/GF Card User Guide

Connector
Pin-outs

Overview

DAG cards have an 8-pin RJ45 connector with two bi-directional RS422
differential circuits, A and B. The PPS signal is carried on circuit A, and the
serial packet is connected to the B circuit.

Pin Assignments

The 8-pin RJ45 connector pin assignments and plugs and sockets are shown
below:

1.

Out A+

2.

Out A-

3.

In A+

4.

In B+

5.

In B-

6.

In A-

7.

Out B+

8.

Out B-

Normally you should connect the GPS input to the A channel input (pins 3
and 6).

The DAG card can also output a synchronization pulse for use when
synchronizing two DAG cards without a GPS input. The synchronization
pulse is output on the Out A channel (pins 1 and 2).

Ethernet Crossover Table

You can use a standard Ethernet crossover cable to connect the two cards as
shown below:

8

1

8

1

Top

Front

8

1

RJ45 Socket

TX_A+ 1 3 RX_A+

TX_A- 2 6 RX-A-

RX_A+ 3 1 TX_A+

RX_B+ 4 7 TX_B+

RX_B- 5 8 TX_B-

RX_A- 6 2 TX_A-

TX_B+ 7 4 RX_B+

TX_B- 8 5 RX_B-

©2005-2006

31

Version 4: August 2006

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Содержание DAG 4.5G2 Card

Страница 1: ...DAG 4 5G2 G4 GF Card User Guide EDM01 18...

Страница 2: ...Endace USA Ltd Suite 220 11495 Sunset Hill Road Reston Virginia 20190 United States of America Phone 1 703 382 0155 Fax 1 703 382 0155 Europe Middle East Africa Endace Europe Ltd Sheraton House Castle...

Страница 3: ...and Materials The product that this manual pertains to may include extra components and materials that are not essential to its basic operation but are necessary to ensure compliance to the product st...

Страница 4: ...EDM 01 18 DAG 4 5G2 G4 GF Card User Guide 2005 2006 Version 4 August 2006...

Страница 5: ...rt Signal Levels 14 Load the FPGA Image 15 Display Current Configuration 15 Auto Negotiation 16 Interface Statistics 17 Chapter 4 Capturing Data 19 Starting a Session 19 Setting Captured Packet Size 1...

Страница 6: ...EDM 01 17 DAG 4 5G2 G4 GF Card User Guide 2005 2006 ii Version 4 August 2006...

Страница 7: ...header only or variable length capture It is capable of transmitting and receiving on each channel simultaneously allowing a single card to operate inline monitoring and transmitting in both directio...

Страница 8: ...d However for convenience a copy of Debian Linux 3 1 Sarge is provided as a bootable ISO image on the CD that is shipped with the DAG card To install either the Linux FreeBSD or Windows operating syst...

Страница 9: ...variable length capture Full line rate transmit 100 capture into host memory at full line rate for IP packets from 48 to 9600 bytes Conditioned clock with PPS input and local synchronization capabili...

Страница 10: ...nterfaces flows directly into the Field Programmable Gate Array FPGA The FPGA contains the packet processor PCI X interface logic and the DAG Universal Clock Kit DUCK timestamp engine The DUCK provide...

Страница 11: ...ard User Guide DAG 4 5G4 The diagram below shows the DAG 4 5G4 card s major components and flow of data DAG 4 5G2 The diagram below shows the DAG 4 5G2 card s major components and flow of data 2005 20...

Страница 12: ...open is the default configuration and is for use in situations where the nature of the event means that traffic must be stopped In fail open mode the network connection will switch to open circuit in...

Страница 13: ...the packet record multiplexer Packet Record Multiplexer ERF MUX The ERF MUX looks at the color information contained in the packet record and determines which receive stream the packet record should b...

Страница 14: ...EDM 01 17 DAG 4 5G2 G4 GF Card User Guide 2005 2006 8 Version 4 August 2006...

Страница 15: ...as appropriate which are included on the CD shipped with the DAG card Inserting the DAG Card Caution It is very important to protect both the PC and the DAG card from damage by electro static dischar...

Страница 16: ...echanical chassis attached to the circuit board Transceiver unit which may be inserted into the chassis Note You must select the correct transceiver type to match the optical parameters of the network...

Страница 17: ...Change the splitter ratio if power is too high or too low Splitter Losses Splitters have the insertion losses either marked on their packaging or described in their accompanying documentation General...

Страница 18: ...EDM 01 17 DAG 4 5G2 G4 GF Card User Guide 2005 2006 12 Version 4 August 2006...

Страница 19: ...d has a set of requirements associated with it relating to the type of cable maximum allowable distance etc Note If you are unsure about which of the options listed below apply to your network please...

Страница 20: ...e shown below 4 pin socket for PPS input FPGA successfully programmed PPS In Card is receiving a time synchronization signal Data capture in progress Port A has link Port B has link A B SFP Ports PPS...

Страница 21: ...rt A nic noeql 1000 Mbps drop_count 0 enablea Port B nic noeql 1000 Mbps drop_count 0 enableb GPP slen 1536 varlen PCI Burst Manager 133MHz buffer size 128 rx_streams 1 tx_streams 1 nodrop Memory Stre...

Страница 22: ...32 bit CRC value from the packet terf_strip32 or sends packet as is noterf_strip Number of packets dropped during current session Resets to 0 if session is restarted Enables or disables the port for c...

Страница 23: ...hows no link on either port A or port B Port Link PLink RFault LOF LOS A 0 0 0 1 1 B 0 0 0 1 1 A 0 0 0 1 1 B 0 0 0 1 1 Link The example below shows a valid link on both port A and port B Port Link PLi...

Страница 24: ...EDM 01 17 DAG 4 5G2 G4 GF Card User Guide 2005 2006 18 Version 4 August 2006...

Страница 25: ...agsnap d0 v o tracefile Note You can use v to provide user information during a capture session although you may want to omit it for automated trace runs By default dagsnap will run indefinitely but c...

Страница 26: ...ed length novarlen mode the card will capture all packets at the same length Any packet that is longer than the slen value will be truncated to that size in the same way as for varlen capture However...

Страница 27: ...the following message displays on the PC screen kernel dagN pbm safety net reached 0xNNNNNNNN The same message is also printed to log var log messages In addition when the PC buffer fills the Data Cap...

Страница 28: ...ig d0 mem 64 64 Note You can not change the stream memory allocations while packet capture or transmission is in progress Explicit Packet Transmission The operating system does not recognize the DAG c...

Страница 29: ...s For DAG 3 x default 32MB card dagmem For DAG 4 x or 6 x use more memory per card E G dagmem dsize 128m For Windows the upper limit is 32MB This is usually sufficient however if you do need to increa...

Страница 30: ...EDM 01 17 DAG 4 5G2 G4 GF Card User Guide 2005 2006 24 Version 4 August 2006...

Страница 31: ...inated universal time UTC You can obtain an accurate time reference by connecting an external clock to the DAG card using the time synchronization connector Alternatively you can use the host PCs cloc...

Страница 32: ...bits that are not active being set to zero In this way the interpretation of the timestamp does not need to change when higher resolution clock hardware is available Example Below is example code show...

Страница 33: ...Note By default all DAG cards listen for synchronization signals on their RS 422 port and do not output any signal to that port dagclock d0 muxin rs422 muxout none status Synchronized Threshold 596ns...

Страница 34: ...d 1 Longest Sequence Missed 1 start Thu Apr 28 14 55 20 2005 host Thu Apr 28 14 59 06 2005 dag Thu Apr 28 14 59 06 2005 Connecting the Time Distribution Server You can connect the TDS 2 module to the...

Страница 35: ...921ns Failures 0 Resyncs 0 error Freq 1836ppb Phase 605ns Worst Freq 143377ppb Worst Phase 88424ns crystal Actual 49999347Hz Synthesized 16777216Hz input Total 87039 Bad 0 Singles Missed 0 Longest Seq...

Страница 36: ...No active input Free running Note The slave card configuration is not shown as the default configuration will work Synchronizing with Host To prevent the DAG card clock time stamps drifting against UT...

Страница 37: ...5 In B 6 In A 7 Out B 8 Out B Normally you should connect the GPS input to the A channel input pins 3 and 6 The DAG card can also output a synchronization pulse for use when synchronizing two DAG card...

Страница 38: ...EDM 01 17 DAG 4 5G2 G4 GF Card User Guide 2005 2006 32 Version 4 August 2006...

Страница 39: ...f ERF records with each record describing one packet An ERF file consists only of ERF records there is no special file header which allows concatenation and splitting to be performed arbitrarily on ER...

Страница 40: ...Record length Total length of the record transferred over the PCI bus to storage rlen Depending upon the ERF type this 16 bit field is either a loss counter of color field The loss counter records th...

Страница 41: ...7 filter 1 etc 14 hlb0 CRC calculation output bit 15 hlb1 parity calculation output bit Note Because both the Type 2 and Type 16 Ethernet record header occupies 18 bytes instead of the standard 16 by...

Страница 42: ...EDM 01 17 DAG 4 5G2 G4 GF Card User Guide 2005 2006 36 Version 4 August 2006...

Страница 43: ...operating system version DAG software version package in use Any compiler errors or warnings when building DAG driver or tools For Linux and FreeBSD messages generated when DAG device driver is loaded...

Страница 44: ...EDM 01 17 DAG 4 5G2 G4 GF Card User Guide 2005 2006 38 Version 4 August 2006...

Страница 45: ...sion Date Reason 1 2 3 April 2006 DAG 4 5GF information added Changes to formatting and layout 4 August 2006 DAG 4 5GF information expanded Separate FPGA images for DAG 4 5G2 GF and DAG 4 5G4 Standard...

Страница 46: ...EDM 01 17 DAG 4 5G2 G4 GF Card User Guide 2005 2006 40 Version 4 August 2006...

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