EMBRON Hatteland HT20 70 Series, Руководство пользователя

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134 Appendix
IND100077-274
WatchDog Timer function
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Publication Release Date: Jun 06, 2019
Version 0.71
5. WATCH DOG TIMER
The Watchdog Timer of the NCT6102D / NCT6104D / NCT6106D consists of an 8-bit programmable time-out
counter and a control and status register. GPIO0, GPIO2, GPIO3, GPIO5, GPIO6, GPIO7 provides an
alternative WDT1 function. This function can be configured by the relative GPIO control register. The units of
Watchdog Timer counter can be selected at Logical Device 8, CR[F0h], bit[3]. The time-out value is set at
Logical Device 8, CR[F1h], default is 4. Writing zero disables the Watchdog Timer function. Writing any non-
zero value to this register causes the counter to load this value into the Watchdog Timer counter and start
counting down.
When Watchdog Timer 1 time-out event is occurring, GPIO0 bit[1], [5], GPIO2, bit[3], [7], GPIO3 bit[1], [5],
GPIO5 bit[0], [4], GPIO6 bit[7], GPIO7 bit[0], will trigger a low pluse apporx 100mS. Also the event could go to
pin77 WDTO#. In other words, when the value is counted down to zero, the timer stops, and the NCT6102D /
NCT6104D / NCT6106D sets the WDT1 status bit in Logical Device 8, CR[F2h], bit[4]. Writing a zero will clear
the status bit. It. This bit will also be cleared if LRESET# or PWROK# signal is asserted.
The Watchdog Timer 2 of the NCT6102D / NCT6104D / NCT6106D consists of an 8-bit programmable time-
out counter register (Logic Device D, CR[E2h]) and status register (Logic Device D, CR[E4h] bit7). The timeout
event will trigger PWROK pin to gerenate a low pulse when Logic Device D, CRE3[bit0] is timer count down
start bit. When Logic Device D, CRE3[bit0] set to one, the timer will start count down, until this bit is written to
zero.
Watchdog Timer I related registers are listed below.
Watchdog Timer I has four registers in Logic Device 8. When CR30h bit0=1, Watchdog Timer circuit is
activated, then CRF5, F6, and F7h are meaningful. Watchdog Timer reset source selection is located at Logic
Device A, CRE7h, bit3.
Logical Device Number
Register address Register Description
Logical Device 8 CR30h, bit0 Watchdog Timer I circuit enable / disable
Logical Device 8 CRF0h Watchdog Timer I Control Mode Register
Logical Device 8 CRF1h Watchdog Timer I Counter Register
Logical Device 8 CRF2h Watchdog Timer I Control & Status Register
Logical Device A CRE7h, bit3 Watchdog Timer I reset source is LRESET# or
PWROK
5.1 Enable Timer
(1) CR30h bit0 = 1, enable Watchdog Timer I circuit.
(2) Configure CRF0h for time unit or other options.
(3) Set time limit into CRF1h then hardware will auto count down. New time limit value overwriting is
acceptable. When CRF1h counts down to 0x0, hardware outputs timeout event on both flag (CRF2h bit4)
and pin (via GPIO).
(4) Check then clear CRF2h bit4 (watchdog timeout flag), the timer will restart counting and de-assert pin (via
GPIO).
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Publication Release Date: Jun 06, 2019
Version 0.71
5.2 Disable Timer
(1) Set 0x0 to CRF1h, stop Watchdog Timer I counting.
(2) CR30h bit0 = 0, disable Watchdog Timer I circuit if no longer use.
5.3 Application Note
(1) When Watchdog Timer I is counting, if want to terminate, BIOS or program MUST stop timer (set 0x0 to
CRF1h) first then call platform reset.
(2) Watchdog Timer I function is reset by LRESET# or PWROK. Cold reset (front panel reset button), warm
reset (CTRL-ALT-DEL), or any application that drives LRESET# event, Watchdog Timer I would be reset.
(3) When Watchdog timeout, the WDTO pin (via GPIO) keeps asserting until flag (CRF2h bit4) is cleared to 0.
6. SMBUS MASTER – MANUAL MODE
6.1 Hardware
SIO NCT6106D pin94/96 can be SMBus Master.
Please note SIO SMBus Master works at S0 state only.
6.2 Software
CR1B bit[1:0] = 01b //set pin.94/96 to be SMBus Master interface
SMBus Master Manual Mode Programming Flow
(1) Assign a I/O base address for SIO SMBus Master operation
Logic Device B, CR62=02h, CR63=A0h
//assign I/O base address 0x2A0h for SIO
Logic Device B, CR30=01h //enable SIO SMBus Master decode
BIOS add I/O address 0x2A0h to chipset generic I/O decoder.
The following extracted section below are available in the full documentation at our website. Please visit:
https://www.hattelandtechnology.com/hubfs/pdf/misc/nct6106d_programming_guide_v071.pdf