Elma JetKit-3010, Руководство пользователя

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USER MANUAL JetKit-3010 ELMA.COM
www.elma.com EMBEDDED BOARDS
2.4.4 Memory Subsystem
The Memory Subsystem (MSS) provides access to local DRAM, SysRAM, and provides a SyncPoint
Interface for inter-processor signaling. The memory subsystem supports full-speed I/O coherence
by routing requests through a scalable coherence fabric. It also supports a comprehensive set of
safety and security mechanisms.
Structurally, the MSS consists of:
1. MSS Data Backbone - routes requests from clients to the MSS Hub and responses from MSS
Hub to the clients.
2. MSS Hub - receives and arbitrates among client requests, performs SMMU translation, and
sends requests to the MCF.
3. Memory Controller Fabric (MCF) - performs security checks, feeds I/O coherent requests to
the Scalable Coherence Fabric (SCF), and directs requests to the multiple memory channels.
4. Memory Controller (MC) Channels - row sorter/arbiter and DRAM controllers.
5. DRAM IO - channel-to-pad fabric, DRAM I/O pads, and PLLs.
Xavier™ series modules integrate a 256-bit wide LPDDR4X memory interface implemented as eight
32-bit channels with x16 subpartitions. The memory controller provides a single read or write
command and row address to both sub-partitions in the channel to transfer 64 bytes, but provides
three independent column address bits to each sub-partition, allowing it access different 32 byte
sectors of a GOB between the sub-partitions. It provides connections between a wide variety of
clients, supporting their bandwidth, latency, quality-of-service needs and any special ordering
requirements that are needed. The MSS supports a variety of security and safety features and
address translation for clients that use virtual addresses.
Table 4 - LPDDR4x Memory Bus
Size Maximum Bandwidth Maximum Bus Frequency ECC Support
32GB 136.5GB/s 2133MHz Enabled by software
Features:
- LPDDR4X: x32 DRAM chips
- 256-bit wide data bus
- Low Latency Path and Fast Read/Response Path Support for the CPU Complex Cluster
- Support for low-power modes:
o
Software controllable entry/exit from: self-refresh, power down, deep power down
o
Hardware dynamic entry/exit from: power down, self-refresh
o
Pads use DPD-mode during idle periods
- High-bandwidth interface to the integrated Volta GPU
- Full-speed IO coherence with bypass for Isochronous (ISO) traffic
- System Memory-Management Unit (SMMU) for address translation based on the ARM
SMMU-500
- High-bandwidth PCIe ordered writes
- AES-XTS encryption with 128-bit key
- DRAM ECC (enabled by software)
o
SEC (Single Error Correction)
o
DED (Double Error Detection)
o
Parity protection support