EKF SC1-ALLEGRO, Руководство пользователя

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User Guide • SC1-ALLEGRO •
CompactPCI ® Serial
CPU Board • Intel® i7-3xxx Processor
Configuration Jumpers
Configuration PCI Express Switch (DS-P)
The link width and transfer rate of the PCI Express interfaces attached to the local expansion
connector P-PCIE is configurable by two DIP switches (DS-P) located on the backside of the
SC1-ALLEGRO. Note that changes in PCIe link configuration are honoured by the SC1-ALLEGRO not
before a system reset was performed.
DS-P PCIe Link Width
1 2 PCIe Switch
Upstream
CPCI Serial
1)
J-PCIE
OFF OFF 4 Lanes @ 5GT/s 4 Links x 1 Lane @ 5GT/s 4 Links x 1 Lane @ 5GT/s
ON OFF 4 Lanes @ 5GT/s 4 Links x 1 Lane @ 5GT/s 1 Link x 4 Lanes @ 5GT/s
OFF ON 4 Lanes @ 2.5GT/s 4 Links x 1 Lane @ 2.5GT/s 4 Links x 1 Lane @ 2.5GT/s
ON ON 4 Lanes @ 2.5GT/s 4 Links x 1 Lane @ 2.5GT/s 1 Link x 4 Lanes @ 2.5GT/s
1)
Consists to the non fat pipe slots, generally periphery slots 3 to 6.
When the port on J-PCIE is configured as single link, the PCIe switch may size down the link width to
x2 or x1 by auto-negotiation.
The following table shows the factory settings of DS-P with different side boards mounted to the
SC1-ALLEGRO:
Side Board DS-P PCIe Link Width
1 2 J-PCIE
None OFF OFF 4 Links x 1 Lane @ 5GT/s
CCI-RAP OFF OFF 4 Links x 1 Lane @ 5GT/s
CCK-MARIMBA ON OFF 1 Link x 4 Lanes @ 5GT/s
CCL-CAPELLA ON OFF 1 Link x 4 Lanes @ 5GT/s
CCO-CONCERT OFF ON 4 Links x 1 Lane @ 2.5GT/s
PCS-BALLET OFF OFF 4 Links x 1 Lane @ 5GT/s
ON
1
2
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