EKF SC1-ALLEGRO, Руководство пользователя

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User Guide • SC1-ALLEGRO •
CompactPCI ® Serial
CPU Board • Intel® i7-3xxx Processor
Read/Clear Status Register 1
Write: SMBus Address 0xB2
Read: SMBus Address 0xB3
Bit Description CMD_STAT1
7 RESERVED
Always read as 0
6 WDGRST
0=Normal operation
1=Last system reset may be caused by a watchdog time-out
5 WDGHT
0=Normal operation
1=The watchdog already has elapsed half of its time-out period
4 PF5PS
0=Normal operation
1=Last system reset may be caused by a power failure of the +V5PS voltage regulator
3 PF133S
0=Normal operation
1=Last system reset may be caused by a power failure of the +V1.05S or +V3.3S voltages
2 PF133M
0=Normal operation
1=Last system reset may be caused by a power failure of the +V1.05M or +V3.3M voltages
1 PF33A
0=Normal operation
1=Last system reset may be caused by a power failure of the +V3.3A voltage regulator
0 PF33S
0=Normal operation
1=Last system reset may be caused by a power failure of the +V3.3S voltage regulator
Except of WDGHT the bits in this register are sticky, i.e. their state will be kept even if a system reset
occurs. To clear the bits a write to the register with arbitrary data may be performed.
Read PLD Revision Register
Write: Not allowed
Read: SMBus Address 0xC1
Bit Description CMD_PLDREV
7:0 PLDREV
Read PLD Revison Number
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