APPENDIX A: Registers for PCIe8g3 S5
Registers, UI
EDT, Inc.
2017 January 04
23
0x6A Serial Master Interface Write [15–8]
0x6B Reference Clock Control
0x6C Sync Trigger Control and Status
0x6D SPI Data
Access / Notes:
8-bit read-write / STRATIX5_I2C_WRITE_DATA_UPPER
Bit
Access
Name
Description
15–8
RW
[no name]
This register [bits 15–8] works with
0x67 Serial Master Interface Write [7–0].
Write data to the serial slave.
Access / Notes:
8-bit read-write / STRATIX5_EXT_PLL
Bit
Access
Name
Description
7
RW
[no name]
Assert to reset the external PLL for all four interfaces.
6–4
–
–
Reserved.
3–0
RW
[no name]
Set to select the local reference crystal as the source for each respective interface on the external PLL;
otherwise, use the recovered clock as the source.
Bit 3 = Port 3
Bit 2 = Port 2
Bit 1 = Port 1
Bit 0 = Port 0
Access / Notes:
8-bit read-write / STRATIX5_SYNC_REG
Bit
Access
Name
Description
7–5
–
–
Reserved.
4
R only
STRATIX5_SYNC_
IN
Status of external synchronization trigger.
3–1
–
–
Reserved.
0
RW
STRATIX5_SYNC_
OUT
Set to send the synchronization trigger.
Access / Notes:
8-bit read-write / SPI_DATA
Bit
Access
Name
Description
7–0
RW
[no name]
If read, bits read from the input FIFO.
If written, bits write to the output FIFO.
