E m b e d d e d S o l u t i o n s P g 9 o f 2 0
Register Definitions
Control Register
Ip_cf_cntl $00 IP-CF Control Register Port read/write
ip_cf_cntl
DATA BIT
DESCRIPTION
15-5
spare
4
0 = 32 MHz, 1 = 8 MHz
3
spare
2
0 = not force interrupt, 1= force interrrupt
1
0 = not enabled master interrupt
0
0 = not Reset IDE, 1 = reset IDE
FIGURE 2
IP-CF CONTROL REGISTER 0 BIT MAP
1. All bits are active low and are reset on power-up.
2. The state-machine which converts from IP to IDE and vice-versa can be optimized to
the 8 or 32 MHz clock. At 32 MHz more wait-states are required. If running at 8 MHz
the additional wait-states can be removed for improved performance.
3. The force interrupt bit when set can cause an interrupt to the host. The master
interrupt enable must also be set. The force interrupt bit can be used to cause an
interrupt for test or software development purposes.
4. The master interrupt enable when set allows the force interrupt or the
CompactFLASH interrupt to be passed to the host. The interrupt should be cleared at
the source.
5. The Reset IDE bit can be used to reset the CompactFLASH slots. Reset on the IDE
bus is active high.
Vector
Ip_cf_vect $02 IP-CF Interrupt Vector Port
The Interrupt vector for the IP-CF is stored in this byte wide register. This read/write
register is initialized to ‘xxFF’ upon power-on reset. The vector is stored in the odd byte
location [D7..0]. The vector should be initialized before the interrupt is enabled or the
mask is lowered. The interrupt is automatically cleared when the CPU acknowledges
the interrupt.
